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AJvYcCWjfMGjzBpp7EV9tqbpDJjvuUvARUILZWvH9Jti48qEMhQ6hr016oN4hj0wsINMCiUdVRFMCjd+lc2Bmam5bonLvaZU5UbZp85CDRPc X-Gm-Message-State: AOJu0Yw0o1Ck20AFwIQn/6o0/SulFpS8g7DZlYTYNGHse8w/wyP5/uAA 8BhVD05NEHFSavo1ae1VfMiWKVKopN7qkgRzFBq3rEIjp3txn8Z5a8DQXd+SsAI= X-Google-Smtp-Source: AGHT+IEr8LsxGh5AtfyyS0a/VJvNay3v21KtD4xp8rzGfwrFFB2jCTneu+QwIAFkZhP6LQiVmKRkuQ== X-Received: by 2002:a05:600c:470f:b0:41b:d8ef:8dcd with SMTP id 5b1f17b1804b1-42164a2e9fcmr53880555e9.28.1717998731427; Sun, 09 Jun 2024 22:52:11 -0700 (PDT) Received: from [192.168.50.4] ([82.78.167.189]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-421cc89e055sm25464975e9.13.2024.06.09.22.52.08 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 09 Jun 2024 22:52:09 -0700 (PDT) Message-ID: <0c8f65e0-866d-4858-9acb-521003198c5e@tuxon.dev> Date: Mon, 10 Jun 2024 08:52:07 +0300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 02/15] pinctrl: renesas: pinctrl-rzg2l: Rename B0WI to BOWI Content-Language: en-US To: Prabhakar , Geert Uytterhoeven , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Biju Das , Claudiu Beznea , Fabrizio Castro , Paul Barker , Lad Prabhakar References: <20240530173857.164073-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20240530173857.164073-3-prabhakar.mahadev-lad.rj@bp.renesas.com> From: claudiu beznea In-Reply-To: <20240530173857.164073-3-prabhakar.mahadev-lad.rj@bp.renesas.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 30.05.2024 20:38, Prabhakar wrote: > From: Lad Prabhakar > > Fix the typo B0WI -> BOWI to match with the RZ/G2L HW manual. > > Reported-by: Geert Uytterhoeven > Signed-off-by: Lad Prabhakar Tested-by: Claudiu Beznea # on RZ/G3S > --- > v2->v3 > - New patch > --- > drivers/pinctrl/renesas/pinctrl-rzg2l.c | 18 +++++++++--------- > 1 file changed, 9 insertions(+), 9 deletions(-) > > diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c > index f784169abf11..169986022a73 100644 > --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c > +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c > @@ -131,7 +131,7 @@ > #define PVDD_1800 1 /* I/O domain voltage <= 1.8V */ > #define PVDD_3300 0 /* I/O domain voltage >= 3.3V */ > > -#define PWPR_B0WI BIT(7) /* Bit Write Disable */ > +#define PWPR_BOWI BIT(7) /* Bit Write Disable */ > #define PWPR_PFCWE BIT(6) /* PFC Register Write Enable */ > > #define PM_MASK 0x03 > @@ -478,8 +478,8 @@ static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl, > writeb(reg & ~BIT(pin), pctrl->base + PMC(off)); > > /* Set the PWPR register to allow PFC register to write */ > - writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */ > - writel(PWPR_PFCWE, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=1 */ > + writel(0x0, pctrl->base + regs->pwpr); /* BOWI=0, PFCWE=0 */ > + writel(PWPR_PFCWE, pctrl->base + regs->pwpr); /* BOWI=0, PFCWE=1 */ > > /* Select Pin function mode with PFC register */ > reg = readl(pctrl->base + PFC(off)); > @@ -487,8 +487,8 @@ static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl, > writel(reg | (func << (pin * 4)), pctrl->base + PFC(off)); > > /* Set the PWPR register to be write-protected */ > - writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */ > - writel(PWPR_B0WI, pctrl->base + regs->pwpr); /* B0WI=1, PFCWE=0 */ > + writel(0x0, pctrl->base + regs->pwpr); /* BOWI=0, PFCWE=0 */ > + writel(PWPR_BOWI, pctrl->base + regs->pwpr); /* BOWI=1, PFCWE=0 */ > > /* Switch to Peripheral pin function with PMC register */ > reg = readb(pctrl->base + PMC(off)); > @@ -2520,8 +2520,8 @@ static void rzg2l_pinctrl_pm_setup_pfc(struct rzg2l_pinctrl *pctrl) > const struct rzg2l_register_offsets *regs = &hwcfg->regs; > > /* Set the PWPR register to allow PFC register to write. */ > - writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */ > - writel(PWPR_PFCWE, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=1 */ > + writel(0x0, pctrl->base + regs->pwpr); /* BOWI=0, PFCWE=0 */ > + writel(PWPR_PFCWE, pctrl->base + regs->pwpr); /* BOWI=0, PFCWE=1 */ > > /* Restore port registers. */ > for (u32 port = 0; port < nports; port++) { > @@ -2565,8 +2565,8 @@ static void rzg2l_pinctrl_pm_setup_pfc(struct rzg2l_pinctrl *pctrl) > } > > /* Set the PWPR register to be write-protected. */ > - writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */ > - writel(PWPR_B0WI, pctrl->base + regs->pwpr); /* B0WI=1, PFCWE=0 */ > + writel(0x0, pctrl->base + regs->pwpr); /* BOWI=0, PFCWE=0 */ > + writel(PWPR_BOWI, pctrl->base + regs->pwpr); /* BOWI=1, PFCWE=0 */ > } > > static int rzg2l_pinctrl_suspend_noirq(struct device *dev)