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b=E5gor6cwaUh8xITx87DXOvoAhGGHRCIdf1YNlOsmSHrrUPIOI84N9P5OaW1v15PBwrTnEjNYqkXvXOXL7Eba0ivjISTFWkheMkPkKYEPXle+i/L4zg7Nf1xXsxdwdX0KGq/R4D8WYJ43qyRmEvIk+EEssEv4eyQ87VuDjuiiJcw= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=amd.com; Received: from PH7PR12MB5712.namprd12.prod.outlook.com (2603:10b6:510:1e3::13) by MW3PR12MB4361.namprd12.prod.outlook.com (2603:10b6:303:5a::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8655.22; Fri, 18 Apr 2025 04:49:30 +0000 Received: from PH7PR12MB5712.namprd12.prod.outlook.com ([fe80::2efc:dc9f:3ba8:3291]) by PH7PR12MB5712.namprd12.prod.outlook.com ([fe80::2efc:dc9f:3ba8:3291%6]) with mapi id 15.20.8655.021; Fri, 18 Apr 2025 04:49:30 +0000 Message-ID: <0c9f534d-a782-4e42-ae44-5d6ac9b51d25@amd.com> Date: Fri, 18 Apr 2025 10:19:19 +0530 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 3/5] perf/x86/amd/uncore: Use hrtimer for handling overflows To: Stephane Eranian Cc: linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, namhyung@kernel.org, mark.rutland@arm.com, alexander.shishkin@linux.intel.com, jolsa@kernel.org, irogers@google.com, adrian.hunter@intel.com, kan.liang@linux.intel.com, tglx@linutronix.de, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, songliubraving@meta.com, ravi.bangoria@amd.com, ananth.narayan@amd.com References: <8ecf5fe20452da1cd19cf3ff4954d3e7c5137468.1744906694.git.sandipan.das@amd.com> Content-Language: en-US From: Sandipan Das In-Reply-To: Content-Type: text/plain; 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It should be >> noted that the hrtimer duration should be lesser than the shortest time >> it takes for a counter to overflow for this approach to be effective. >> > The problem I see is that the number of uncore PMU varies a lot based > on the CPU model, in particular due to the L3 PMU. > Is there a timer armed per CCX or only a global one that will generate > IPI to all other CPUs? > For L3 PMU, its on a per-CCX basis. >> Signed-off-by: Sandipan Das >> --- >> arch/x86/events/amd/uncore.c | 63 ++++++++++++++++++++++++++++++++++++ >> 1 file changed, 63 insertions(+) >> >> diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c >> index 010024f09f2c..e09bfbb4a4cd 100644 >> --- a/arch/x86/events/amd/uncore.c >> +++ b/arch/x86/events/amd/uncore.c >> @@ -21,6 +21,7 @@ >> #define NUM_COUNTERS_NB 4 >> #define NUM_COUNTERS_L2 4 >> #define NUM_COUNTERS_L3 6 >> +#define NUM_COUNTERS_MAX 64 >> >> #define RDPMC_BASE_NB 6 >> #define RDPMC_BASE_LLC 10 >> @@ -38,6 +39,10 @@ struct amd_uncore_ctx { >> int refcnt; >> int cpu; >> struct perf_event **events; >> + unsigned long active_mask[BITS_TO_LONGS(NUM_COUNTERS_MAX)]; >> + int nr_active; >> + struct hrtimer hrtimer; >> + u64 hrtimer_duration; >> }; >> >> struct amd_uncore_pmu { >> @@ -87,6 +92,42 @@ static struct amd_uncore_pmu *event_to_amd_uncore_pmu(struct perf_event *event) >> return container_of(event->pmu, struct amd_uncore_pmu, pmu); >> } >> >> +static enum hrtimer_restart amd_uncore_hrtimer(struct hrtimer *hrtimer) >> +{ >> + struct amd_uncore_ctx *ctx; >> + struct perf_event *event; >> + int bit; >> + >> + ctx = container_of(hrtimer, struct amd_uncore_ctx, hrtimer); >> + >> + if (!ctx->nr_active || ctx->cpu != smp_processor_id()) >> + return HRTIMER_NORESTART; >> + >> + for_each_set_bit(bit, ctx->active_mask, NUM_COUNTERS_MAX) { >> + event = ctx->events[bit]; >> + event->pmu->read(event); >> + } >> + >> + hrtimer_forward_now(hrtimer, ns_to_ktime(ctx->hrtimer_duration)); >> + return HRTIMER_RESTART; >> +} >> + >> +static void amd_uncore_start_hrtimer(struct amd_uncore_ctx *ctx) >> +{ >> + hrtimer_start(&ctx->hrtimer, ns_to_ktime(ctx->hrtimer_duration), >> + HRTIMER_MODE_REL_PINNED_HARD); >> +} >> + >> +static void amd_uncore_cancel_hrtimer(struct amd_uncore_ctx *ctx) >> +{ >> + hrtimer_cancel(&ctx->hrtimer); >> +} >> + >> +static void amd_uncore_init_hrtimer(struct amd_uncore_ctx *ctx) >> +{ >> + hrtimer_setup(&ctx->hrtimer, amd_uncore_hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL_HARD); >> +} >> + >> static void amd_uncore_read(struct perf_event *event) >> { >> struct hw_perf_event *hwc = &event->hw; >> @@ -117,18 +158,26 @@ static void amd_uncore_read(struct perf_event *event) >> >> static void amd_uncore_start(struct perf_event *event, int flags) >> { >> + struct amd_uncore_pmu *pmu = event_to_amd_uncore_pmu(event); >> + struct amd_uncore_ctx *ctx = *per_cpu_ptr(pmu->ctx, event->cpu); >> struct hw_perf_event *hwc = &event->hw; >> >> + if (!ctx->nr_active++) >> + amd_uncore_start_hrtimer(ctx); >> + >> if (flags & PERF_EF_RELOAD) >> wrmsrl(hwc->event_base, (u64)local64_read(&hwc->prev_count)); >> >> hwc->state = 0; >> + __set_bit(hwc->idx, ctx->active_mask); >> wrmsrl(hwc->config_base, (hwc->config | ARCH_PERFMON_EVENTSEL_ENABLE)); >> perf_event_update_userpage(event); >> } >> >> static void amd_uncore_stop(struct perf_event *event, int flags) >> { >> + struct amd_uncore_pmu *pmu = event_to_amd_uncore_pmu(event); >> + struct amd_uncore_ctx *ctx = *per_cpu_ptr(pmu->ctx, event->cpu); >> struct hw_perf_event *hwc = &event->hw; >> >> wrmsrl(hwc->config_base, hwc->config); >> @@ -138,6 +187,11 @@ static void amd_uncore_stop(struct perf_event *event, int flags) >> event->pmu->read(event); >> hwc->state |= PERF_HES_UPTODATE; >> } >> + >> + if (!--ctx->nr_active) >> + amd_uncore_cancel_hrtimer(ctx); >> + >> + __clear_bit(hwc->idx, ctx->active_mask); >> } >> >> static int amd_uncore_add(struct perf_event *event, int flags) >> @@ -490,6 +544,9 @@ static int amd_uncore_ctx_init(struct amd_uncore *uncore, unsigned int cpu) >> goto fail; >> } >> >> + amd_uncore_init_hrtimer(curr); >> + curr->hrtimer_duration = 60LL * NSEC_PER_SEC; >> + >> cpumask_set_cpu(cpu, &pmu->active_mask); >> } >> >> @@ -879,12 +936,18 @@ static int amd_uncore_umc_event_init(struct perf_event *event) >> >> static void amd_uncore_umc_start(struct perf_event *event, int flags) >> { >> + struct amd_uncore_pmu *pmu = event_to_amd_uncore_pmu(event); >> + struct amd_uncore_ctx *ctx = *per_cpu_ptr(pmu->ctx, event->cpu); >> struct hw_perf_event *hwc = &event->hw; >> >> + if (!ctx->nr_active++) >> + amd_uncore_start_hrtimer(ctx); >> + >> if (flags & PERF_EF_RELOAD) >> wrmsrl(hwc->event_base, (u64)local64_read(&hwc->prev_count)); >> >> hwc->state = 0; >> + __set_bit(hwc->idx, ctx->active_mask); >> wrmsrl(hwc->config_base, (hwc->config | AMD64_PERFMON_V2_ENABLE_UMC)); >> perf_event_update_userpage(event); >> } >> -- >> 2.43.0 >>