From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CAF7CC54EBE for ; Tue, 10 Jan 2023 06:49:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230467AbjAJGtK (ORCPT ); Tue, 10 Jan 2023 01:49:10 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57608 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229747AbjAJGss (ORCPT ); Tue, 10 Jan 2023 01:48:48 -0500 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 31BBF30558; Mon, 9 Jan 2023 22:48:46 -0800 (PST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A3D17AD7; Mon, 9 Jan 2023 22:49:27 -0800 (PST) Received: from [10.162.42.6] (unknown [10.162.42.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E00AE3F71A; Mon, 9 Jan 2023 22:48:38 -0800 (PST) Message-ID: <0cb01d4a-884e-0ee3-120e-b2df92b92a15@arm.com> Date: Tue, 10 Jan 2023 12:18:35 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.2.2 Subject: Re: [PATCH v4 1/8] perf: arm_spe: Use feature numbering for PMSEVFR_EL1 defines Content-Language: en-US To: Rob Herring , Peter Zijlstra , Will Deacon , Mark Rutland , Catalin Marinas , Marc Zyngier , James Morse , Alexandru Elisei , Suzuki K Poulose , Oliver Upton , Ingo Molnar , Arnaldo Carvalho de Melo , Alexander Shishkin , Jiri Olsa , Namhyung Kim Cc: Mark Brown , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-perf-users@vger.kernel.org, James Clark References: <20220825-arm-spe-v8-7-v4-0-327f860daf28@kernel.org> <20220825-arm-spe-v8-7-v4-1-327f860daf28@kernel.org> From: Anshuman Khandual In-Reply-To: <20220825-arm-spe-v8-7-v4-1-327f860daf28@kernel.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 1/10/23 00:56, Rob Herring wrote: > Similar to commit 121a8fc088f1 ("arm64/sysreg: Use feature numbering for > PMU and SPE revisions") use feature numbering instead of architecture > versions for the PMSEVFR_EL1 Res0 defines. > > Tested-by: James Clark > Signed-off-by: Rob Herring Reviewed-by: Anshuman Khandual > --- > v4: > - Rebase on v6.2-rc1 > v3: > - No change > v2: > - New patch > --- > arch/arm64/include/asm/sysreg.h | 6 +++--- > drivers/perf/arm_spe_pmu.c | 4 ++-- > 2 files changed, 5 insertions(+), 5 deletions(-) > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index 1312fb48f18b..c4ce16333750 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -273,11 +273,11 @@ > #define SYS_PMSFCR_EL1_ST_SHIFT 18 > > #define SYS_PMSEVFR_EL1 sys_reg(3, 0, 9, 9, 5) > -#define SYS_PMSEVFR_EL1_RES0_8_2 \ > +#define PMSEVFR_EL1_RES0_IMP \ > (GENMASK_ULL(47, 32) | GENMASK_ULL(23, 16) | GENMASK_ULL(11, 8) |\ > BIT_ULL(6) | BIT_ULL(4) | BIT_ULL(2) | BIT_ULL(0)) > -#define SYS_PMSEVFR_EL1_RES0_8_3 \ > - (SYS_PMSEVFR_EL1_RES0_8_2 & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11))) > +#define PMSEVFR_EL1_RES0_V1P1 \ > + (PMSEVFR_EL1_RES0_IMP & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11))) > > #define SYS_PMSLATFR_EL1 sys_reg(3, 0, 9, 9, 6) > #define SYS_PMSLATFR_EL1_MINLAT_SHIFT 0 > diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c > index 00e3a637f7b6..65cf93dcc8ee 100644 > --- a/drivers/perf/arm_spe_pmu.c > +++ b/drivers/perf/arm_spe_pmu.c > @@ -677,11 +677,11 @@ static u64 arm_spe_pmsevfr_res0(u16 pmsver) > { > switch (pmsver) { > case ID_AA64DFR0_EL1_PMSVer_IMP: > - return SYS_PMSEVFR_EL1_RES0_8_2; > + return PMSEVFR_EL1_RES0_IMP; > case ID_AA64DFR0_EL1_PMSVer_V1P1: > /* Return the highest version we support in default */ > default: > - return SYS_PMSEVFR_EL1_RES0_8_3; > + return PMSEVFR_EL1_RES0_V1P1; > } > } > >