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AJvYcCUjL2mFbeODDYdZYNS1lB9KUxdG9YoQ5+pZxEabyxdaOsJXigavrKLanDQOXL4jOeMuVKct+53wcDQBZnbxIe7l8JvGzWEH95bDG/r4 X-Gm-Message-State: AOJu0YyHlbmjwru6Gu1/9jeksrafxOZbStoR0Vj2oD+1lTZf+3kcH8Fb 4orMU8s6E2CMFAXInqkIm25rOijR9VZzGhC4GKEbpL7HrGvsAUCUC03PtFsdbZA= X-Google-Smtp-Source: AGHT+IFm7J11+wdhrgMT/TGaX0Rc7thLKL2Wg4raKr9nb+KKvQo276Bk7ZpHF10bnd8Q9L9dV3BTgw== X-Received: by 2002:a05:6214:19ce:b0:6b0:4201:3840 with SMTP id 6a1803df08f44-6b5b7148e19mr79621526d6.40.1719847625201; Mon, 01 Jul 2024 08:27:05 -0700 (PDT) Received: from [100.64.0.1] ([147.124.94.167]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6b59e581ed4sm33779996d6.69.2024.07.01.08.27.02 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 01 Jul 2024 08:27:04 -0700 (PDT) Message-ID: <0cc13581-5cc4-4a25-a943-7a896f42da4c@sifive.com> Date: Mon, 1 Jul 2024 10:27:01 -0500 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 03/13] riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree To: Charlie Jenkins Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Conor Dooley , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Jonathan Corbet , Shuah Khan , Guo Ren , Evan Green , Andy Chiu , Jessica Clarke References: <20240619-xtheadvector-v3-0-bff39eb9668e@rivosinc.com> <20240619-xtheadvector-v3-3-bff39eb9668e@rivosinc.com> Content-Language: en-US From: Samuel Holland In-Reply-To: <20240619-xtheadvector-v3-3-bff39eb9668e@rivosinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Hi Charlie, On 2024-06-19 6:57 PM, Charlie Jenkins wrote: > The D1/D1s SoCs support xtheadvector so it can be included in the > devicetree. Also include vlenb for the cpu. > > Signed-off-by: Charlie Jenkins > Reviewed-by: Conor Dooley > --- > arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 3 ++- The other C906/C910/C920-based SoCs need devicetree updates as well, although they don't necessarily need to be part of this series: - sophgo/cv18xx.dtsi - sophgo/sg2042-cpus.dtsi - thead/th1520.dtsi > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > index 64c3c2e6cbe0..6367112e614a 100644 > --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > @@ -27,7 +27,8 @@ cpu0: cpu@0 { > riscv,isa = "rv64imafdc"; The ISA string should be updated to keep it in sync with riscv,isa-extensions. Regards, Samuel > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", > - "zifencei", "zihpm"; > + "zifencei", "zihpm", "xtheadvector"; > + thead,vlenb = <128>; > #cooling-cells = <2>; > > cpu0_intc: interrupt-controller { >