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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTEyMDA0NiBTYWx0ZWRfX29BZhFA/u3w9 IdE+54tFbk1RBpaNP4W/AQVC2/wnEiZ6glgV/9IVSs6K52voPws81n+n0ErV8phVKe3c+GcMOcA 2/vZUfpWkWW0MzEiGyfb1vJ9eEKaMLYZ34ZHPEca7LtKlBTwN9OaxrlyQraB1wK7kf/5hZLt8yn 5ofNoDSdBCWO4VOVKpk1B1uEqsWTJ9ns5tWV9Vi/3OR7wfTwCBKY2JQuG82ENUuzvSk9YJUP3rf 7Ch60m1TrJTfZzlg/tgnG+ATPt/VsB9GygSCY0A2HqN2jDp93Sy1crReRW/99sylC425zwAUX6G xBVwDmUcqV8bM+SXgKUHklfmmhdsFARY0Bsm9N22TRyx0u9awvR5xYT29DvgCpkuEgFd+ES6l/l /SBV7R6ujrkpz3vJkkwDhO4zSFdHHfU3uquuIsIOYJFY7tqpFdtwYMVQ8+3t4kPdhk1Ku5rMNxx kDza31Anp3UpXa0zlkA== X-Proofpoint-ORIG-GUID: J6Oj_ri3czESw8EBw103zzLlYoTFavq1 X-Authority-Analysis: v=2.4 cv=YocChoYX c=1 sm=1 tr=0 ts=69648fd1 cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=j4ogTh8yFefVWWEFDRgCtg==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=UqCG9HQmAAAA:8 a=iG3OsJvFCE3OXJAcmq8A:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: J6Oj_ri3czESw8EBw103zzLlYoTFavq1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-12_01,2026-01-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 spamscore=0 lowpriorityscore=0 malwarescore=0 phishscore=0 clxscore=1011 impostorscore=0 adultscore=0 priorityscore=1501 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2601120046 Hi Varada, On 1/6/2026 4:24 PM, Varadarajan Narayanan wrote: > From: Vignesh Viswanathan > > Add support to bring up hexagon based WCSS using secure PIL. All IPQxxxx > SoCs support secure Peripheral Image Loading (PIL). > > Secure PIL image is signed firmware image which only trusted software such > as TrustZone (TZ) can authenticate and load. Linux kernel will send a > Peripheral Authentication Service (PAS) request to TZ to authenticate and > load the PIL images. > > In order to avoid overloading the existing WCSS driver or PAS driver, we > came up with this new PAS based IPQ WCSS driver. > > Signed-off-by: Vignesh Viswanathan > Signed-off-by: Manikanta Mylavarapu > Signed-off-by: Gokul Sriram Palanisamy > Signed-off-by: George Moussalem > [ Dropped ipq5424 support ] > Signed-off-by: Varadarajan Narayanan > --- > v8: Dropped ipq5424 support. > The comments related to 'use_tmelcom' in [1] not applicable > [1] https://lore.kernel.org/linux-arm-msm/72f0d4f7-8d8a-4fc5-bac2-8094e971a0e3@oss.qualcomm.com/ > Changed copyright for drivers/remoteproc/qcom_q6v5_wcss_sec.c > --- > drivers/remoteproc/Kconfig | 19 ++ > drivers/remoteproc/Makefile | 1 + > drivers/remoteproc/qcom_q6v5_wcss_sec.c | 328 ++++++++++++++++++++++++ > include/linux/remoteproc.h | 2 + > 4 files changed, 350 insertions(+) > create mode 100644 drivers/remoteproc/qcom_q6v5_wcss_sec.c > [...] > diff --git a/drivers/remoteproc/qcom_q6v5_wcss_sec.c b/drivers/remoteproc/qcom_q6v5_wcss_sec.c > new file mode 100644 > index 000000000000..10fe3391decb > --- /dev/null > +++ b/drivers/remoteproc/qcom_q6v5_wcss_sec.c > @@ -0,0 +1,328 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. > + */ > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include "qcom_common.h" > +#include "qcom_q6v5.h" > +#include "qcom_pil_info.h" > + > +#define WCSS_CRASH_REASON 421 > + > +#define WCSS_PAS_ID 0x6 > +#define MPD_WCSS_PAS_ID 0xd > + > +#define Q6_WAIT_TIMEOUT (5 * HZ) > + > +struct wcss_sec { > + struct device *dev; > + struct qcom_rproc_glink glink_subdev; > + struct qcom_rproc_ssr ssr_subdev; > + struct qcom_q6v5 q6; > + phys_addr_t mem_phys; > + phys_addr_t mem_reloc; > + void *mem_region; > + size_t mem_size; > + const struct wcss_data *desc; > + > + struct mbox_client mbox_client; > + struct mbox_chan *mbox_chan; > + void *metadata; > + size_t metadata_len; above member variables are now unused. [...] > + > +static int wcss_sec_probe(struct platform_device *pdev) > +{ > + const struct wcss_data *desc = of_device_get_match_data(&pdev->dev); > + const char *fw_name = NULL; > + struct wcss_sec *wcss; > + struct clk *sleep_clk; > + struct clk *int_clk; > + struct rproc *rproc; > + int ret; > + > + ret = of_property_read_string(pdev->dev.of_node, "firmware-name", > + &fw_name); > + if (ret < 0) > + return ret; > + > + rproc = devm_rproc_alloc(&pdev->dev, desc->ss_name, &wcss_sec_ops, > + fw_name, sizeof(*wcss)); > + if (!rproc) { > + dev_err(&pdev->dev, "failed to allocate rproc\n"); > + return -ENOMEM; > + } > + > + wcss = rproc->priv; > + wcss->dev = &pdev->dev; > + wcss->desc = desc; > + > + ret = wcss_sec_alloc_memory_region(wcss); > + if (ret) > + return ret; > + > + sleep_clk = devm_clk_get_optional_enabled(&pdev->dev, "sleep"); > + if (IS_ERR(sleep_clk)) > + return dev_err_probe(&pdev->dev, PTR_ERR(sleep_clk), > + "Failed to get sleep clock\n"); > + > + int_clk = devm_clk_get_optional_enabled(&pdev->dev, "interconnect"); > + if (IS_ERR(int_clk)) > + return dev_err_probe(&pdev->dev, PTR_ERR(int_clk), > + "Failed to get interconnect clock\n"); > + > + ret = qcom_q6v5_init(&wcss->q6, pdev, rproc, > + WCSS_CRASH_REASON, NULL, NULL); > + if (ret) > + return ret; > + > + qcom_add_glink_subdev(rproc, &wcss->glink_subdev, desc->ss_name); > + qcom_add_ssr_subdev(rproc, &wcss->ssr_subdev, desc->ss_name); > + > + rproc->auto_boot = false; > + rproc->dump_conf = RPROC_COREDUMP_INLINE; > + rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE); > + > + ret = devm_rproc_add(&pdev->dev, rproc); > + if (ret) On failure, please include qcom_remove_glink_subdev(rproc, &wcss->glink_subdev); qcom_remove_ssr_subdev(rproc, &wcss->ssr_subdev);Regards, Regards, Gokul > + return ret; > + > + platform_set_drvdata(pdev, rproc); > + > + return 0; > +} > + > +static void wcss_sec_remove(struct platform_device *pdev) > +{ > + struct rproc *rproc = platform_get_drvdata(pdev); > + struct wcss_sec *wcss = rproc->priv; > + > + mbox_free_channel(wcss->mbox_chan); > + qcom_remove_glink_subdev(rproc, &wcss->glink_subdev); > + qcom_remove_ssr_subdev(rproc, &wcss->ssr_subdev); > + qcom_q6v5_deinit(&wcss->q6); > +} > + > +static const struct wcss_data wcss_sec_ipq5332_res_init = { > + .pasid = MPD_WCSS_PAS_ID, > + .ss_name = "q6wcss", > +}; > + > +static const struct wcss_data wcss_sec_ipq9574_res_init = { > + .pasid = WCSS_PAS_ID, > + .ss_name = "q6wcss", > +}; > + > +static const struct of_device_id wcss_sec_of_match[] = { > + { .compatible = "qcom,ipq5018-wcss-sec-pil", .data = &wcss_sec_ipq5332_res_init }, > + { .compatible = "qcom,ipq5332-wcss-sec-pil", .data = &wcss_sec_ipq5332_res_init }, > + { .compatible = "qcom,ipq9574-wcss-sec-pil", .data = &wcss_sec_ipq9574_res_init }, > + { }, > +}; > +MODULE_DEVICE_TABLE(of, wcss_sec_of_match); > + > +static struct platform_driver wcss_sec_driver = { > + .probe = wcss_sec_probe, > + .remove = wcss_sec_remove, > + .driver = { > + .name = "qcom-wcss-secure-pil", > + .of_match_table = wcss_sec_of_match, > + }, > +}; > +module_platform_driver(wcss_sec_driver); > + > +MODULE_DESCRIPTION("Hexagon WCSS Secure Peripheral Image Loader"); > +MODULE_LICENSE("GPL"); > diff --git a/include/linux/remoteproc.h b/include/linux/remoteproc.h > index b4795698d8c2..7b2159853345 100644 > --- a/include/linux/remoteproc.h > +++ b/include/linux/remoteproc.h > @@ -472,6 +472,7 @@ enum rproc_dump_mechanism { > * @node: list node related to the rproc segment list > * @da: device address of the segment > * @size: size of the segment > + * @io_ptr: ptr to store the ioremapped dump segment > * @priv: private data associated with the dump_segment > * @dump: custom dump function to fill device memory segment associated > * with coredump > @@ -483,6 +484,7 @@ struct rproc_dump_segment { > dma_addr_t da; > size_t size; > > + void *io_ptr; > void *priv; > void (*dump)(struct rproc *rproc, struct rproc_dump_segment *segment, > void *dest, size_t offset, size_t size);