From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753164AbeDQS4Z (ORCPT ); Tue, 17 Apr 2018 14:56:25 -0400 Received: from smtprelay4.synopsys.com ([198.182.47.9]:59303 "EHLO smtprelay.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752941AbeDQS4V (ORCPT ); Tue, 17 Apr 2018 14:56:21 -0400 Subject: Re: [PATCH v5 07/10] PCI: dwc: Define maximum number of vectors To: Gustavo Pimentel , , , , , , , CC: , , References: From: Joao Pinto Message-ID: <0cf5b436-7c7e-93b4-c13d-2490e19b9a41@synopsys.com> Date: Tue, 17 Apr 2018 19:56:15 +0100 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.1.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Language: pt-PT Content-Transfer-Encoding: 8bit X-Originating-IP: [10.107.15.26] Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Gustavo, Às 3:34 PM de 4/17/2018, Gustavo Pimentel escreveu: > Adds a callback that defines the maximum number of vectors that can be use > by the Root Complex. > > Since this is a parameter associated to each SoC IP setting, makes sense to > be configurable and easily visible to future modifications. > > The designware IP supports a maximum of 256 vectors. > > Signed-off-by: Gustavo Pimentel > --- > Change v1->v2: > - Nothing changed, just to follow the patch set version. > Change v2->v3: > - Nothing changed, just to follow the patch set version. > Changes v3->v4: > - Nothing changed, just to follow the patch set version. > Changes v4->v5: > - Nothing changed, just to follow the patch set version. > > drivers/pci/dwc/pcie-designware-plat.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/drivers/pci/dwc/pcie-designware-plat.c b/drivers/pci/dwc/pcie-designware-plat.c > index efc315c..5937fed 100644 > --- a/drivers/pci/dwc/pcie-designware-plat.c > +++ b/drivers/pci/dwc/pcie-designware-plat.c > @@ -48,8 +48,14 @@ static int dw_plat_pcie_host_init(struct pcie_port *pp) > return 0; > } > > +static void dw_plat_set_num_vectors(struct pcie_port *pp) > +{ > + pp->num_vectors = MAX_MSI_IRQS; > +} > + > static const struct dw_pcie_host_ops dw_plat_pcie_host_ops = { > .host_init = dw_plat_pcie_host_init, > + .set_num_vectors = dw_plat_set_num_vectors, > }; > > static int dw_plat_pcie_establish_link(struct dw_pcie *pci) > Yes, in our reference plat driver we should target all the available IRQs. Thanks! Acked-by: Joao Pinto