From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 447E4C433EF for ; Wed, 13 Apr 2022 03:01:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231731AbiDMDDY (ORCPT ); Tue, 12 Apr 2022 23:03:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40286 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229721AbiDMDDT (ORCPT ); Tue, 12 Apr 2022 23:03:19 -0400 X-Greylist: delayed 368 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Tue, 12 Apr 2022 20:00:55 PDT Received: from mail-m17640.qiye.163.com (mail-m17640.qiye.163.com [59.111.176.40]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AA3832656C; Tue, 12 Apr 2022 20:00:55 -0700 (PDT) Received: from [172.16.12.69] (unknown [58.22.7.114]) by mail-m17640.qiye.163.com (Hmail) with ESMTPA id D15D35403EB; Wed, 13 Apr 2022 10:54:44 +0800 (CST) Message-ID: <0cf83ec0-29d3-fbde-0b7d-9d58d210f0a4@rock-chips.com> Date: Wed, 13 Apr 2022 10:54:45 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Cc: shawn.lin@rock-chips.com, linux-rockchip@lists.infradead.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v1 2/4] PCI: dwc: rockchip: add legacy interrupt support Content-Language: en-GB To: Peter Geis , Lorenzo Pieralisi , Rob Herring , =?UTF-8?Q?Krzysztof_Wilczy=c5=84ski?= , Bjorn Helgaas , Heiko Stuebner References: <20220412185751.124783-1-pgwipeout@gmail.com> <20220412185751.124783-3-pgwipeout@gmail.com> From: Shawn Lin In-Reply-To: <20220412185751.124783-3-pgwipeout@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-HM-Spam-Status: e1kfGhgUHx5ZQUtXWQgPGg8OCBgUHx5ZQUlOS1dZCBgUCR5ZQVlLVUtZV1 kWDxoPAgseWUFZKDYvK1lXWShZQUlKS0tKN1dZLVlBSVdZDwkaFQgSH1lBWUJLHhpWH0gaSxlPHU 1ITx1KVRMBExYaEhckFA4PWVdZFhoPEhUdFFlBWU9LSFVKSktISkNVS1kG X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6PU06Dhw*Nz0*GD8RSB0uOAwe Lw8aFCpVSlVKTU9CQ0pDT0NOT0lKVTMWGhIXVQgTGgwVVRcSFTsJFBgQVhgTEgsIVRgUFkVZV1kS C1lBWU5DVUlJVUxVSkpPWVdZCAFZQUlDS083Bg++ X-HM-Tid: 0a8020d841c5d995kuwsd15d35403eb Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Peter, 在 2022/4/13 2:57, Peter Geis 写道: > The legacy interrupts on the rk356x pcie controller are handled by a > single muxed interrupt. Add irq domain support to the pcie-dw-rockchip > > +static void rockchip_pcie_legacy_int_handler(struct irq_desc *desc) > +{ > + struct irq_chip *chip = irq_desc_get_chip(desc); > + struct rockchip_pcie *rockchip = irq_desc_get_handler_data(desc); > + struct device *dev = rockchip->pci.dev; > + u32 reg; > + u32 hwirq; > + u32 virq; > + > + chained_irq_enter(chip, desc); > + > + reg = rockchip_pcie_readl_apb(rockchip, 0x8); > + Overall it looks good except that 0x8 has a name, PCIE_CLIENT_INTR_STATUS_LEGACY. BTW, If you consider adding more support to it, for instance, enable/disable/affinity? The downstream kernel finished these for better fitting for function driver usage.