From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3BD0E3AEB4A for ; Tue, 12 May 2026 14:26:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778595987; cv=none; b=cj56n8BuIt0plpxKa8O4g2giE9TgoxLFf9kCGobEUKmniNBGKUgZfCA+fc9DqoDTkRWsuccJvxIETWymdgyMrtnL596ebiBneWAXNJeRkKGSzYS6AkMXqbaiXDr/P6nhC1CWHaT/70dZ+YwPbDI0cs1GVIIKjswf4M+iFciNu1E= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778595987; c=relaxed/simple; bh=qpMdxz9TgEC1c+q/t9iob6swPriRIunzLAqBFHJNEyU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=t2oIkxWwl+/uXpUAuGKSrf7yn0D3SEivN1GzpTohp/uEhiTK1QJJpjKDObG9lqaeiJABlcWsMVfw9giwmxun18PScQaYsEmCZrFhnO23BCmqPukd6NZQrwuuHOuTNoZYW8ZnQ5ZY20Zxa3qLCBP7CUTDoU20dxkcPIscURnDNU0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Yl5wkkL+; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Yl5wkkL+" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 64547C2BCB0; Tue, 12 May 2026 14:26:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1778595987; bh=qpMdxz9TgEC1c+q/t9iob6swPriRIunzLAqBFHJNEyU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Yl5wkkL+ifgh5ntiohXlc4oImksZEJtnMNpFgf/bLrsTtLv24PT9zVovGypxO4lrD /pdzXW0J8698aqeiLHnhOObtr474ZJsCW6V+GQgd7tAHAlL5nPPhkqDb3Y7qaw7ASX RQM5bcjybkxtSH7VMRvEHCu/iI5LdKGT+su+kg7Qia8IPpMxwSGX8rDOUJduSn10Zy OapMd16OxPxWv7DLI202bLeFZufIShSRfNNcOsnMMBMzbq9Kk6V7oUmorUXp/qSj0M qecrduONL+4pkEV9xByI3IpTHUb6PC6IGRn9k6zwD1LYzlNJHBC1ezcLPJuQey+ylv vRv4gRvu62zSw== From: "Naveen N Rao (AMD)" To: Cc: Thomas Gleixner , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Nikunj A Dadhania , Manali Shukla , Bharata B Rao , Subject: [PATCH v2 3/3] x86/apic: Drop APIC_EILVT_NR_MAX and switch to using apic_eilvt_count Date: Tue, 12 May 2026 19:49:17 +0530 Message-ID: <0cf8b5dc628faaca27920994eb9ad229d94e7d1c.1778594390.git.naveen@kernel.org> X-Mailer: git-send-email 2.54.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Switch to using apic_eilvt_count as the maximum EILVT register count. Since this value is no longer a compile-time constant, update eilvt_offsets to be dynamically allocated. Signed-off-by: Naveen N Rao (AMD) Tested-by: Manali Shukla --- arch/x86/include/asm/apicdef.h | 1 - arch/x86/kernel/apic/apic.c | 7 +++++-- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/apicdef.h b/arch/x86/include/asm/apicdef.h index ba7657e75ad1..32a242ae0455 100644 --- a/arch/x86/include/asm/apicdef.h +++ b/arch/x86/include/asm/apicdef.h @@ -140,7 +140,6 @@ #define APIC_IER 0x480 #define APIC_EILVTn(n) (0x500 + 0x10 * n) #define APIC_EILVT_NR_AMD_10H 4 -#define APIC_EILVT_NR_MAX APIC_EILVT_NR_AMD_10H #define APIC_BASE (fix_to_virt(FIX_APIC_BASE)) #define APIC_BASE_MSR 0x800 diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index ecbf15399399..0313989e1632 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -341,7 +341,7 @@ static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) * necessarily a BIOS bug. */ -static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; +static atomic_t *eilvt_offsets; unsigned int apic_eilvt_count __ro_after_init; EXPORT_SYMBOL_FOR_KVM(apic_eilvt_count); @@ -356,7 +356,7 @@ static unsigned int reserve_eilvt_offset(int offset, unsigned int new) { unsigned int rsvd, vector; - if (offset >= APIC_EILVT_NR_MAX) + if (!eilvt_offsets || offset >= apic_eilvt_count) return ~0; rsvd = atomic_read(&eilvt_offsets[offset]); @@ -419,6 +419,9 @@ static __init void init_eilvt(void) if (!apic_eilvt_count && boot_cpu_data.x86_vendor == X86_VENDOR_AMD) apic_eilvt_count = APIC_EILVT_NR_AMD_10H; + + if (apic_eilvt_count) + eilvt_offsets = kzalloc_objs(atomic_t, apic_eilvt_count); } /* -- 2.54.0