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b=VIl+Xy7ZRs9RYlN50x2DiApOwDw8REs4DTR7IbV5dqlw4kcHLEYrfMdjYpihuFPhWZ+hMW84xmPaxSvfPLton2PJAnHCKzhNsXUxmEH4PkYYk4liRMzzdX23ocsxnbu37CrYbhuMO2h4UYXjU/rqaALSqPNNTXrwRYgVwTErfBo= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=amd.com; Received: from DS0PR12MB6390.namprd12.prod.outlook.com (2603:10b6:8:ce::7) by CH2PR12MB4246.namprd12.prod.outlook.com (2603:10b6:610:a9::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8293.16; Thu, 26 Dec 2024 17:07:17 +0000 Received: from DS0PR12MB6390.namprd12.prod.outlook.com ([fe80::38ec:7496:1a35:599f]) by DS0PR12MB6390.namprd12.prod.outlook.com ([fe80::38ec:7496:1a35:599f%3]) with mapi id 15.20.8293.000; Thu, 26 Dec 2024 17:07:17 +0000 Message-ID: <0d552424-150e-4b92-8326-0fe6387e0ce6@amd.com> Date: Thu, 26 Dec 2024 11:07:13 -0600 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 14/15] cxl/pci: Add support to assign and clear pci_driver::cxl_err_handlers To: Jonathan Cameron Cc: linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, nifan.cxl@gmail.com, dave@stgolabs.net, dave.jiang@intel.com, alison.schofield@intel.com, vishal.l.verma@intel.com, dan.j.williams@intel.com, bhelgaas@google.com, mahesh@linux.ibm.com, ira.weiny@intel.com, oohall@gmail.com, Benjamin.Cheatham@amd.com, rrichter@amd.com, nathan.fontenot@amd.com, Smita.KoralahalliChannabasappa@amd.com, lukas@wunner.de, PradeepVineshReddy.Kodamati@amd.com, Li Ming References: <20241211234002.3728674-1-terry.bowman@amd.com> <20241211234002.3728674-15-terry.bowman@amd.com> <20241224185000.00001a5f@huawei.com> Content-Language: en-US From: "Bowman, Terry" In-Reply-To: <20241224185000.00001a5f@huawei.com> Content-Type: text/plain; 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This >> function will assign the default handlers for a CXL PCIe Port device. >> >> When the CXL Port (cxl_port or cxl_dport) is destroyed the device's >> pci_driver::cxl_err_handlers must be set to NULL indicating they should no >> longer be used. >> >> Create cxl_clear_port_error_handlers() and register it to be called >> when the CXL Port device (cxl_port or cxl_dport) is destroyed. >> >> Signed-off-by: Terry Bowman >> --- >> drivers/cxl/core/pci.c | 40 ++++++++++++++++++++++++++++++++++++++++ >> 1 file changed, 40 insertions(+) >> >> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c >> index 3294ad5ff28f..9734a4c55b29 100644 >> --- a/drivers/cxl/core/pci.c >> +++ b/drivers/cxl/core/pci.c >> @@ -841,8 +841,38 @@ static bool cxl_port_error_detected(struct pci_dev *pdev) >> return __cxl_handle_ras(&pdev->dev, ras_base); >> } >> >> +static const struct cxl_error_handlers cxl_port_error_handlers = { >> + .error_detected = cxl_port_error_detected, >> + .cor_error_detected = cxl_port_cor_error_detected, >> +}; >> + >> +static void cxl_assign_port_error_handlers(struct pci_dev *pdev) >> +{ >> + struct pci_driver *pdrv; >> + >> + if (!pdev || !pdev->driver) >> + return; >> + >> + pdrv = pdev->driver; > What stops a race here? It's fiddly to remove that driver but > it can be done. At least I think we are messing withe portdrv > but this is such a fiddly stack I'm not 100% sure. > >> + pdrv->cxl_err_handler = &cxl_port_error_handlers; >> +} >> + >> +static void cxl_clear_port_error_handlers(void *data) >> +{ >> + struct pci_dev *pdev = data; >> + struct pci_driver *pdrv; >> + >> + if (!pdev || !pdev->driver) >> + return; >> + >> + pdrv = pdev->driver; > Likewise. Smells like a possible race. > >> + pdrv->cxl_err_handler = NULL; >> +} >> + I can add a get_device()/put_device() for both cxl_clear_port_error_handlers() and cxl_assign_port_error_handlers() to prevent operating on a recently destroyed pci_dev. Is that sufficient? Regards, Terry >> void cxl_uport_init_ras_reporting(struct cxl_port *port) >> { >> + struct pci_dev *pdev = to_pci_dev(port->uport_dev); >> + >> /* uport may have more than 1 downstream EP. Check if already mapped. */ >> if (port->uport_regs.ras) >> return; >> @@ -853,6 +883,9 @@ void cxl_uport_init_ras_reporting(struct cxl_port *port) >> dev_err(&port->dev, "Failed to map RAS capability.\n"); >> return; >> } >> + >> + cxl_assign_port_error_handlers(pdev); >> + devm_add_action_or_reset(port->uport_dev, cxl_clear_port_error_handlers, pdev); >> } >> EXPORT_SYMBOL_NS_GPL(cxl_uport_init_ras_reporting, CXL); >> >> @@ -864,6 +897,7 @@ void cxl_dport_init_ras_reporting(struct cxl_dport *dport) >> { >> struct device *dport_dev = dport->dport_dev; >> struct pci_host_bridge *host_bridge = to_pci_host_bridge(dport_dev); >> + struct pci_dev *pdev = to_pci_dev(dport_dev); >> >> dport->reg_map.host = dport_dev; >> if (dport->rch && host_bridge->native_aer) { >> @@ -880,6 +914,12 @@ void cxl_dport_init_ras_reporting(struct cxl_dport *dport) >> dev_err(dport_dev, "Failed to map RAS capability.\n"); >> return; >> } >> + >> + if (dport->rch) >> + return; >> + >> + cxl_assign_port_error_handlers(pdev); >> + devm_add_action_or_reset(dport_dev, cxl_clear_port_error_handlers, pdev); >> } >> EXPORT_SYMBOL_NS_GPL(cxl_dport_init_ras_reporting, CXL); >>