From: "Mi, Dapeng" <dapeng1.mi@linux.intel.com>
To: Zide Chen <zide.chen@intel.com>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Namhyung Kim <namhyung@kernel.org>,
Ian Rogers <irogers@google.com>,
Adrian Hunter <adrian.hunter@intel.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Andi Kleen <ak@linux.intel.com>,
Eranian Stephane <eranian@google.com>
Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org
Subject: Re: [PATCH V3 2/8] perf/x86/intel/uncore: Fix refcnt and other cleanups
Date: Fri, 12 Jun 2026 08:52:04 +0800 [thread overview]
Message-ID: <0d5867c1-3d14-4c9a-805a-453b66a24fa9@linux.intel.com> (raw)
In-Reply-To: <20260611160033.66760-3-zide.chen@intel.com>
LGTM. Thanks.
Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
On 6/12/2026 12:00 AM, Zide Chen wrote:
> Fix typo UNCORE_BOX_FLAG_INITIATED to UNCORE_BOX_FLAG_INITIALIZED.
>
> Rename the 'id' parameter in uncore_box_{ref,unref}() to 'die' to
> reflect its actual meaning and be consistent with other functions.
>
> box->refcnt is incremented in the PCI PMU register path but has never
> been checked or decremented. Although for PCI PMUs box->refcnt
> effectively tracks only a single user, add atomic_dec_return() in the
> PCI PMU unregister path to make the reference counting complete and
> consistent.
>
> Signed-off-by: Zide Chen <zide.chen@intel.com>
> ---
> v3:
> - Instead of removing atomic_inc(&box->refcnt) in PMU register, add
> the corresponding atomic_dec_return(&box->refcnt) in PMU unregister.
> (Dapeng)
> v2:
> - Don't rename pmu->activeboxes and keep its semantics because in
> uncore_pci_remove() path, uncore_pci_pmu_unregister() won't be
> called for non-active boxes.
> - Since pmu->activeboxes keeps its name, don't need to rename
> box->refcnt to box->cpu_refcnt.
> ---
> arch/x86/events/intel/uncore.c | 16 +++++++++-------
> arch/x86/events/intel/uncore.h | 6 +++---
> 2 files changed, 12 insertions(+), 10 deletions(-)
>
> diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c
> index b69b6a21d46b..21c8ed1628cb 100644
> --- a/arch/x86/events/intel/uncore.c
> +++ b/arch/x86/events/intel/uncore.c
> @@ -1255,8 +1255,10 @@ static void uncore_pci_pmu_unregister(struct intel_uncore_pmu *pmu, int die)
> pmu->boxes[die] = NULL;
> if (atomic_dec_return(&pmu->activeboxes) == 0)
> uncore_pmu_unregister(pmu);
> - uncore_box_exit(box);
> - kfree(box);
> + if (atomic_dec_return(&box->refcnt) == 0) {
> + uncore_box_exit(box);
> + kfree(box);
> + }
> }
>
> static void uncore_pci_remove(struct pci_dev *pdev)
> @@ -1518,7 +1520,7 @@ static void uncore_change_context(struct intel_uncore_type **uncores,
> uncore_change_type_ctx(*uncores, old_cpu, new_cpu);
> }
>
> -static void uncore_box_unref(struct intel_uncore_type **types, int id)
> +static void uncore_box_unref(struct intel_uncore_type **types, int die)
> {
> struct intel_uncore_type *type;
> struct intel_uncore_pmu *pmu;
> @@ -1529,7 +1531,7 @@ static void uncore_box_unref(struct intel_uncore_type **types, int id)
> type = *types;
> pmu = type->pmus;
> for (i = 0; i < type->num_boxes; i++, pmu++) {
> - box = pmu->boxes[id];
> + box = pmu->boxes[die];
> if (box && box->cpu >= 0 && atomic_dec_return(&box->refcnt) == 0)
> uncore_box_exit(box);
> }
> @@ -1604,14 +1606,14 @@ static int allocate_boxes(struct intel_uncore_type **types,
> }
>
> static int uncore_box_ref(struct intel_uncore_type **types,
> - int id, unsigned int cpu)
> + int die, unsigned int cpu)
> {
> struct intel_uncore_type *type;
> struct intel_uncore_pmu *pmu;
> struct intel_uncore_box *box;
> int i, ret;
>
> - ret = allocate_boxes(types, id, cpu);
> + ret = allocate_boxes(types, die, cpu);
> if (ret)
> return ret;
>
> @@ -1619,7 +1621,7 @@ static int uncore_box_ref(struct intel_uncore_type **types,
> type = *types;
> pmu = type->pmus;
> for (i = 0; i < type->num_boxes; i++, pmu++) {
> - box = pmu->boxes[id];
> + box = pmu->boxes[die];
> if (box && box->cpu >= 0 && atomic_inc_return(&box->refcnt) == 1)
> uncore_box_init(box);
> }
> diff --git a/arch/x86/events/intel/uncore.h b/arch/x86/events/intel/uncore.h
> index c2e5ccb1d72c..bad5d8dec8e0 100644
> --- a/arch/x86/events/intel/uncore.h
> +++ b/arch/x86/events/intel/uncore.h
> @@ -185,7 +185,7 @@ struct intel_uncore_box {
> #define CFL_UNC_CBO_7_PERFEVTSEL0 0xf70
> #define CFL_UNC_CBO_7_PER_CTR0 0xf76
>
> -#define UNCORE_BOX_FLAG_INITIATED 0
> +#define UNCORE_BOX_FLAG_INITIALIZED 0
> /* event config registers are 8-byte apart */
> #define UNCORE_BOX_FLAG_CTL_OFFS8 1
> /* CFL 8th CBOX has different MSR space */
> @@ -559,7 +559,7 @@ static inline u64 uncore_read_counter(struct intel_uncore_box *box,
>
> static inline void uncore_box_init(struct intel_uncore_box *box)
> {
> - if (!test_and_set_bit(UNCORE_BOX_FLAG_INITIATED, &box->flags)) {
> + if (!test_and_set_bit(UNCORE_BOX_FLAG_INITIALIZED, &box->flags)) {
> if (box->pmu->type->ops->init_box)
> box->pmu->type->ops->init_box(box);
> }
> @@ -567,7 +567,7 @@ static inline void uncore_box_init(struct intel_uncore_box *box)
>
> static inline void uncore_box_exit(struct intel_uncore_box *box)
> {
> - if (test_and_clear_bit(UNCORE_BOX_FLAG_INITIATED, &box->flags)) {
> + if (test_and_clear_bit(UNCORE_BOX_FLAG_INITIALIZED, &box->flags)) {
> if (box->pmu->type->ops->exit_box)
> box->pmu->type->ops->exit_box(box);
> }
next prev parent reply other threads:[~2026-06-12 0:52 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-11 16:00 [PATCH v3 0/8] perf/x86/intel/uncore: PMU setup robustness fixes Zide Chen
2026-06-11 16:00 ` [PATCH V3 1/8] perf/x86/intel/uncore: Fix PCI PMU cleanup on setup failure Zide Chen
2026-06-30 9:09 ` [tip: perf/core] " tip-bot2 for Zide Chen
2026-06-11 16:00 ` [PATCH V3 2/8] perf/x86/intel/uncore: Fix refcnt and other cleanups Zide Chen
2026-06-12 0:52 ` Mi, Dapeng [this message]
2026-06-30 9:09 ` [tip: perf/core] " tip-bot2 for Zide Chen
2026-06-11 16:00 ` [PATCH V3 3/8] perf/x86/intel/uncore: Let init_box() callback report failures Zide Chen
2026-06-30 9:09 ` [tip: perf/core] " tip-bot2 for Zide Chen
2026-06-11 16:00 ` [PATCH V3 4/8] perf/x86/intel/uncore: Keep PCI PMUs working when MMIO/MSR setup fails Zide Chen
2026-06-30 9:09 ` [tip: perf/core] " tip-bot2 for Zide Chen
2026-06-11 16:00 ` [PATCH V3 5/8] perf/x86/intel/uncore: Factor out box setup code Zide Chen
2026-06-30 9:09 ` [tip: perf/core] " tip-bot2 for Zide Chen
2026-06-11 16:00 ` [PATCH V3 6/8] perf/x86/intel/uncore: Introduce PMU flags and broken state Zide Chen
2026-06-12 0:53 ` Mi, Dapeng
2026-06-30 9:09 ` [tip: perf/core] " tip-bot2 for Zide Chen
2026-06-11 16:00 ` [PATCH V3 7/8] perf/x86/intel/uncore: Fix uncore_box ref/unref ordering Zide Chen
2026-06-12 0:55 ` Mi, Dapeng
2026-06-30 9:09 ` [tip: perf/core] " tip-bot2 for Zide Chen
2026-06-11 16:00 ` [PATCH V3 8/8] perf/x86/intel/uncore: Implement lazy setup for MSR/MMIO PMUs Zide Chen
2026-06-30 9:09 ` [tip: perf/core] " tip-bot2 for Zide Chen
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