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client-ip=165.204.84.17; helo=satlexmb08.amd.com; pr=C Received: from satlexmb08.amd.com (165.204.84.17) by BN3PEPF0000B36F.mail.protection.outlook.com (10.167.243.166) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9791.0 via Frontend Transport; Fri, 3 Apr 2026 08:13:57 +0000 Received: from satlexmb07.amd.com (10.181.42.216) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Fri, 3 Apr 2026 03:13:57 -0500 Received: from [10.136.42.52] (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server id 15.2.2562.17 via Frontend Transport; Fri, 3 Apr 2026 03:13:55 -0500 Message-ID: <0d781470-e206-4c15-9149-8710b4060493@amd.com> Date: Fri, 3 Apr 2026 13:43:54 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 4/4] sched/rt: Split cpupri_vec->cpumask to per NUMA node to reduce contention To: "Chen, Yu C" , Peter Zijlstra CC: Tim Chen , Pan Deng , , , References: <20260320124003.GU3738786@noisy.programming.kicks-ass.net> <63a095f02428700a7ff2623b8ea81e524a406834.camel@linux.intel.com> <20260324120008.GB3738010@noisy.programming.kicks-ass.net> <138c3f9d-309f-41e6-aa72-a3f6bd713bf0@intel.com> <22072ef8-5aec-49ac-9cc4-8a80bec14261@amd.com> <64649c85-29ab-4f70-a0c4-3c83cbdae2fc@intel.com> <20260402105530.GA3738786@noisy.programming.kicks-ass.net> <93d7eb33-c3a5-4498-bc26-57806b73d9e0@amd.com> <3b66e8e8-07e0-4f3e-a3ba-d97133af5162@intel.com> Content-Language: en-US From: K Prateek Nayak In-Reply-To: <3b66e8e8-07e0-4f3e-a3ba-d97133af5162@intel.com> Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: p8NwaVthacbd1XgKf7x2x/MJKBhuSdNfQag8pTVNcPqC3msMp5gxSGEbtHAbJ+/wKD9TuM+BtNuOqk8eiX7qumPsZsA0makWkF1UW6Y4M+Mfjme+JhFsuKATmaqdmt9u1iEv3vlBezds9FTXwFKP79DldYUoURbn3eUnqDANMMTF/I8syZZbqMJZXri4VusCRFVqb4Zr8/LWYpDjJevv3q8K2frdgC4giKTGtKx93TMQKG2smOKuGjbYVU/ihvRGtQkwonEEd9Bl+WBjnHFHgzgJCthMIDFyhmJG2aShDFhMwu1tW9ApnQO+BJLuZ/t1U5BpgoL5KkzuR86GWudy7Bvzivq3v+KWu1KvUo8v+ewNoFXfk3ByK2hHkRubffJpEW7oFvhSxVq1YRvULNfA07da2ag9C7Li5E2ADwYB2X6Y7PwCSvBQkSPi8TLkcYeB X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Apr 2026 08:13:57.2574 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fc66a1f1-f660-4355-8509-08de9158f42d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B36F.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB9054 Hello Chenyu, On 4/3/2026 11:16 AM, Chen, Yu C wrote: > On 4/2/2026 7:06 PM, K Prateek Nayak wrote: >> Hello Peter, >> >> On 4/2/2026 4:25 PM, Peter Zijlstra wrote: >>> On Thu, Apr 02, 2026 at 10:11:11AM +0530, K Prateek Nayak wrote: >>> >>>> It is still not super clear to me how the logic deals with more than >>>> 128CPUs in a DIE domain because that'll need more than the u64 but >>>> sbm_find_next_bit() simply does: >>>> >>>>      tmp = leaf->bitmap & mask; /* All are u64 */ >>>> >>>> expecting just the u64 bitmap to represent all the CPUs in the leaf. >>>> >>>> If we have, say 256 CPUs per DIE, we get shift(7) and arch_sbm_mask >>>> as 7f (127) which allows a leaf to more than 64 CPUs but we are >>>> using the "u64 bitmap" directly and not: >>>> >>>>      find_next_bit(bitmap, arch_sbm_mask) >>>> >>>> Am I missing something here? >>> >>> Nope. That logic just isn't there, that was left as an exercise to the >>> reader :-) >> >> Ack! Let me go fiddle with that. >> > > Nice catch. I hadn't noticed this since we have fewer than > 64 CPUs per die. Please feel free to send patches to me when > they're available. > > And regarding your other question about the calculation of arch_sbm_shift, > I'm trying to understand why there is a subtraction of 1, should it be: > -       arch_sbm_shift = x86_topo_system.dom_shifts[TOPO_DIE_DOMAIN] - 1; > +       arch_sbm_shift = x86_topo_system.dom_shifts[TOPO_DIE_DOMAIN - 1]; > ? > Are we trying to filer the raw global unique die id? - similar to topo_apicid() > which mask the lower x86_topo_system.dom_shifts[dom - 1]). > > With above change I can get a correct value of leaves (4) rather than (2) in > the original version. Thanks for confirming. I guess that would just be TOPO_TILE_DOMAIN then and would work well on AMD too since that is where the CCX is mapped. I'll get hold of a SPR / use a VM to confirm with 0x1f behavior. I'll post the patches next week since I have to check with Andrea on how the ARM systems have decided to number their SMT threads and whether they requires separate plumbing for arch_sbm_idx_to_cpu(), arch_sbm_cpu_to_idx() or not. -- Thanks and Regards, Prateek