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Thu, 05 Nov 2026 13:58:11 -0800 (PST) Received: from [192.168.1.9] ([106.222.231.155]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1b245b8822fsm23076429c88.2.2026.11.05.13.58.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 05 Nov 2026 13:58:11 -0800 (PST) Message-ID: <0d7cf70f-cc16-4d9f-a53c-7f2f9e3e509d@oss.qualcomm.com> Date: Fri, 6 Nov 2026 03:28:04 +0530 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 07/15] drm/msm/a8xx: Stop getting GMEM_PROTECT from nonctx list To: Rob Clark , dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Alexander Koskovich , Jie Zhang , Bhaskar Reddy Valluru , Nico Angelo Dela Cruz , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , open list References: <20261105203057.66520-1-robin.clark@oss.qualcomm.com> <20261105203057.66520-8-robin.clark@oss.qualcomm.com> Content-Language: en-US From: Akhil P Oommen In-Reply-To: <20261105203057.66520-8-robin.clark@oss.qualcomm.com> Content-Type: text/plain; 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> > @@ -709,7 +706,6 @@ static const struct adreno_reglist_pipe a840_nonctxt_regs[] = { > { REG_A7XX_RB_CCU_CNTL, 0x00000068, BIT(PIPE_BR) }, > /* Partially enable perf clear, Disable DINT to c/z be data forwarding */ > { REG_A7XX_RB_CCU_DBG_ECO_CNTL, 0x00002200, BIT(PIPE_BR) }, > - { REG_A8XX_RB_GC_GMEM_PROTECT, 0x12000000, BIT(PIPE_BR) }, > { REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0x00000007, BIT(PIPE_BR) }, > { REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0x00004000, BIT(PIPE_BR) }, > { REG_A8XX_RBBM_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) }, > @@ -1102,7 +1098,6 @@ static const struct adreno_reglist_pipe a845_nonctxt_regs[] = { > { REG_A7XX_RB_CCU_CNTL, 0x00000068, BIT(PIPE_BR) }, > { REG_A7XX_RB_CCU_DBG_ECO_CNTL, BIT(10) | BIT(9), BIT(PIPE_BR) }, > { REG_A6XX_RB_DBG_ECO_CNTL, BIT(17), BIT(PIPE_BV) | BIT(PIPE_BR) }, > - { REG_A8XX_RB_GC_GMEM_PROTECT, 0x0C000000, BIT(PIPE_BR) }, > { REG_A6XX_RB_RBP_CNTL, BIT(5) | BIT(6), BIT(PIPE_BV) | BIT(PIPE_BR) }, > { REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0x00000007, BIT(PIPE_BR) }, > { REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0x00004000, BIT(PIPE_BR) }, > @@ -1161,7 +1156,6 @@ static const struct adreno_reglist_pipe a850_nonctxt_regs[] = { > { REG_A7XX_RB_CCU_CNTL, 0x00000068, BIT(PIPE_BR) }, > { REG_A7XX_RB_CCU_DBG_ECO_CNTL, BIT(10) | BIT(9), BIT(PIPE_BR) }, > { REG_A6XX_RB_DBG_ECO_CNTL, BIT(17), BIT(PIPE_BV) | BIT(PIPE_BR) }, > - { REG_A8XX_RB_GC_GMEM_PROTECT, 0x12000000, BIT(PIPE_BR) }, > { REG_A6XX_RB_RBP_CNTL, BIT(5) | BIT(6), BIT(PIPE_BV) | BIT(PIPE_BR) }, > { REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0x00000007, BIT(PIPE_BR) }, > { REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0x00004000, BIT(PIPE_BR) }, > diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c > index 59898b49a201..f65bf82e5c21 100644 > --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c > @@ -370,7 +370,7 @@ static void a8xx_set_ubwc_config(struct msm_gpu *gpu) > hbb_lo << 1 | ubwc_mode); > } > > -static void a8xx_nonctxt_config(struct msm_gpu *gpu, u32 *gmem_protect) > +static void a8xx_nonctxt_config(struct msm_gpu *gpu) > { > struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); > struct a6xx_gmu *gmu = &to_a6xx_gpu(adreno_gpu)->gmu; > @@ -390,9 +390,6 @@ static void a8xx_nonctxt_config(struct msm_gpu *gpu, u32 *gmem_protect) > if (!(BIT(pipe_id) & regs[i].pipe)) > continue; > > - if (regs[i].offset == REG_A8XX_RB_GC_GMEM_PROTECT) > - *gmem_protect = regs[i].value; > - > if ((regs[i].offset << 2) >= gmu->mmio_offset) { > gmu_write(gmu, regs[i].offset, regs[i].value); > } else { > @@ -638,7 +635,6 @@ static int hw_init(struct msm_gpu *gpu) > struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); > struct a6xx_gmu *gmu = &a6xx_gpu->gmu; > unsigned int pipe_id, i; > - u32 gmem_protect = 0; > u64 gmem_range_min; > int ret; > > @@ -719,7 +715,7 @@ static int hw_init(struct msm_gpu *gpu) > > gpu_write(gpu, REG_A8XX_UCHE_CLIENT_PF, BIT(7) | 0x1); > > - a8xx_nonctxt_config(gpu, &gmem_protect); > + a8xx_nonctxt_config(gpu); > > /* Enable fault detection */ > gpu_write(gpu, REG_A8XX_RBBM_INTERFACE_HANG_INT_CNTL, BIT(30) | 0xcfffff); > @@ -838,8 +834,8 @@ static int hw_init(struct msm_gpu *gpu) > * GMEM_PROTECT register should be programmed after GPU is transitioned to > * non-secure mode > */ > - a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_RB_GC_GMEM_PROTECT, gmem_protect); > - WARN_ON(!gmem_protect); > + a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_RB_GC_GMEM_PROTECT, > + (adreno_gpu->info->gmem / SZ_4K) << 16); > a8xx_aperture_clear(gpu); > > if (!a6xx_gpu->pwrup_reglist_emitted) {