From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 886EE2FF65B for ; Thu, 9 Apr 2026 19:27:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775762834; cv=none; b=RIgBcGqBFzx3NDaV94OFa0DDTXQuIq+9E+MbX+jkm+MVbXkPMmF6LctxOf7OcodJ1HVnKQNvIfxIJzr8TBSud57he4g+yAIqXJsABTKwENPxJyS1jax+/zO73MkWqbaC2hC2MfzLrCpSMeyk6j0BGpLbPtvQlgJj902+srLuK2g= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775762834; c=relaxed/simple; bh=iABnIMhY/9YZZ6NAxF/2LpNbjszjDQX5oG3aQV1fKdI=; h=Message-ID:Subject:From:To:Cc:Date:In-Reply-To:References: Content-Type:MIME-Version; b=Ew9o2e4QTWpVjop6JvZkykrpQ6ph4rAMMx9O3yd4ty4kkiCZeoVX5uHysxExj03xlfsPEGS4Efdv7h7tF7d3PUlC3SWMt1T0JONwBuKM9+VgWuI+ZOY4TnHyRNMTyZxUqkKUEZhgr73W2Cf7r8s0aTKjNA/P/pQtgEGi+JyH4Bo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=MG/DQ7mw; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="MG/DQ7mw" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1775762832; x=1807298832; h=message-id:subject:from:to:cc:date:in-reply-to: references:content-transfer-encoding:mime-version; bh=iABnIMhY/9YZZ6NAxF/2LpNbjszjDQX5oG3aQV1fKdI=; b=MG/DQ7mwt7SXsjZH6gCmMRDGZ+/tWxNnrQKm6mCjzYxzoB1+kit/PBAS 1nFzTbDywS5VWyRk3YUMZTBfmNq6FagGMN24L+en0DX2x149Oon1vpekS DoLOnqO3eDLYQMa1sJ+f9oi94rV7Kk0056Ol4LoAbdJh5d0V/S0od9M/N MN4KHh8HEi8swvuCThnyiLQC6Rys2uznUhbjURJNZq/V33DOrL4QBLIoA 4qlP4cXOay0xnGMej7O+5uA2OKKNqNoE47LuBrvANBgQs3JOecxxmLKwT zMOYOQIRDy1w2W91SN7hNb/D2k66jBAu6xt8xgt/hiZGSuPlQ3KmOl4Hw Q==; X-CSE-ConnectionGUID: R9Ko+ftOTL6DY2rYQyD9DA== X-CSE-MsgGUID: C48dAIK0SGGUOovyXTfeAQ== X-IronPort-AV: E=McAfee;i="6800,10657,11754"; a="80638475" X-IronPort-AV: E=Sophos;i="6.23,170,1770624000"; d="scan'208";a="80638475" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Apr 2026 12:27:12 -0700 X-CSE-ConnectionGUID: A8jQjd+rT1qMsVlgJHXatQ== X-CSE-MsgGUID: kdF7XGRQS2mqpYe2Ahgn8g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,170,1770624000"; d="scan'208";a="251999387" Received: from unknown (HELO [10.241.243.39]) ([10.241.243.39]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Apr 2026 12:27:11 -0700 Message-ID: <0d7e029deb6c5e59199c6e14141778306a17c67f.camel@linux.intel.com> Subject: Re: [Patch v4 16/22] sched/cache: Disable cache aware scheduling for processes with high thread counts From: Tim Chen To: Peter Zijlstra Cc: Ingo Molnar , K Prateek Nayak , "Gautham R . Shenoy" , Vincent Guittot , Chen Yu , Juri Lelli , Dietmar Eggemann , Steven Rostedt , Ben Segall , Mel Gorman , Valentin Schneider , Madadi Vineeth Reddy , Hillf Danton , Shrikanth Hegde , Jianyong Wu , Yangyu Chen , Tingyin Duan , Vern Hao , Vern Hao , Len Brown , Aubrey Li , Zhao Liu , Chen Yu , Adam Li , Aaron Lu , Tim Chen , Josh Don , Gavin Guo , Qais Yousef , Libo Chen , linux-kernel@vger.kernel.org Date: Thu, 09 Apr 2026 12:27:10 -0700 In-Reply-To: <20260409124312.GB3126523@noisy.programming.kicks-ass.net> References: <47cc4cffecdac2770a719c84bec3b459a1256def.1775065312.git.tim.c.chen@linux.intel.com> <20260409124312.GB3126523@noisy.programming.kicks-ass.net> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.58.1 (3.58.1-1.fc43) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Thu, 2026-04-09 at 14:43 +0200, Peter Zijlstra wrote: > On Wed, Apr 01, 2026 at 02:52:28PM -0700, Tim Chen wrote: > > @@ -1507,7 +1513,8 @@ void account_mm_sched(struct rq *rq, struct task_= struct *p, s64 delta_exec) > > */ > > if (time_after(epoch, > > READ_ONCE(mm->sc_stat.epoch) + EPOCH_LLC_AFFINITY_TIMEOUT) || > > - get_nr_threads(p) <=3D 1) { > > + get_nr_threads(p) <=3D 1 || > > + exceed_llc_nr(mm, cpu_of(rq))) { > > if (mm->sc_stat.cpu !=3D -1) > > mm->sc_stat.cpu =3D -1; > > } >=20 > > @@ -1608,6 +1633,13 @@ static void task_cache_work(struct callback_head= *work) > > if (p->flags & PF_EXITING) > > return; > > =20 > > + if (get_nr_threads(p) <=3D 1) { > > + if (mm->sc_stat.cpu !=3D -1) > > + mm->sc_stat.cpu =3D -1; > > + > > + return; > > + } > > + > > if (!zalloc_cpumask_var(&cpus, GFP_KERNEL)) > > return; > > =20 >=20 > > @@ -10105,6 +10144,13 @@ static enum llc_mig can_migrate_llc_task(int s= rc_cpu, int dst_cpu, > > if (cpu < 0 || cpus_share_cache(src_cpu, dst_cpu)) > > return mig_unrestricted; > > =20 > > + /* skip cache aware load balance for single/too many threads */ > > + if (get_nr_threads(p) <=3D 1 || exceed_llc_nr(mm, dst_cpu)) { > > + if (mm->sc_stat.cpu !=3D -1) > > + mm->sc_stat.cpu =3D -1; > > + return mig_unrestricted; > > + } > > + > > if (cpus_share_cache(dst_cpu, cpu)) > > to_pref =3D true; > > else if (cpus_share_cache(src_cpu, cpu)) >=20 > This is what that made me notice that weird get_nr_threads() <=3D 1 thing= . >=20 With a single thread, we already have code like scanning in the same LLC in wake up, and migrate_degrades_locality() to keep it where its cache is hot. Adding a preferred_llc seems unnecessary. Tim