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[91.159.24.186]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5b291e25e5bsm2736698e87.78.2026.07.21.01.17.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 21 Jul 2026 01:17:16 -0700 (PDT) Message-ID: <0da6d314-bfa9-493a-bcc6-8c3b75751d0c@linaro.org> Date: Tue, 21 Jul 2026 11:17:16 +0300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v13 1/2] dt-bindings: phy: qcom: Add CSI2 C-PHY/DPHY schema To: Bryan O'Donoghue , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong Cc: Bryan O'Donoghue , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski References: <20260720-x1e-csi2-phy-v13-0-160c31958863@linaro.org> <20260720-x1e-csi2-phy-v13-1-160c31958863@linaro.org> From: Vladimir Zapolskiy In-Reply-To: <20260720-x1e-csi2-phy-v13-1-160c31958863@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 7/20/26 04:11, Bryan O'Donoghue wrote: > Add a base schema for the MIPI CSI2 PHYs on Qualcomm SoCs. This PHY > supports both DPHY and CPHY operation. A special mode of DPHY operation - > called variously split-mode or combo-mode also allows for two sensors to be > connected to one PHY. > > The submitted binding here describes the DPHY modes of operation only. CPHY > is left to future work. > > Reviewed-by: Krzysztof Kozlowski > Signed-off-by: Bryan O'Donoghue Since there is no changes in dt bindings from v12, all comments from here are still applicable to this version of the changeset: https://lore.kernel.org/linux-arm-msm/20260719-x1e-csi2-phy-v12-0-cc7311326d1b@linaro.org/ > --- > .../bindings/phy/qcom,x1e80100-csi2-phy.yaml | 195 +++++++++++++++++++++ > 1 file changed, 195 insertions(+) > > diff --git a/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml > new file mode 100644 > index 0000000000000..880fe602945cb > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml > @@ -0,0 +1,195 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/qcom,x1e80100-csi2-phy.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm X1E80100 SoC CSI2 PHY > + > +maintainers: > + - Bryan O'Donoghue > + > +description: > + Qualcomm MIPI CSI2 C-PHY/D-PHY combination PHY. Connects MIPI CSI2 sensors > + to Qualcomm's Camera CSI Decoder. The PHY supports both C-PHY and D-PHY > + modes. > + > +properties: > + compatible: > + const: qcom,x1e80100-csi2-phy > + > + reg: > + maxItems: 1 > + > + "#phy-cells": > + const: 1 > + description: > + The single cell specifies the PHY operating mode. This has been reported before, #phy-cells shall be 0, the operation mode is selected by bus-type of endpoints as it is described in video-interfaces.yaml Two competing values are redundant and it opens a door to a wrong hardware description, the technical discussion has not been started yet. > + > + clocks: > + maxItems: 3 > + > + clock-names: > + items: > + - const: core > + - const: timer > + - const: ahb > + > + interrupts: > + maxItems: 1 > + > + operating-points-v2: true > + > + opp-table: > + type: object > + > + power-domains: > + items: > + - description: Titan Top GDSC - Titan ISP Block, Global Distributed Switch Controller. > + - description: MMCX voltage rail > + - description: MXC or MXA voltage rail > + > + power-domain-names: > + items: > + - const: top > + - const: mmcx > + - const: mx > + > + vdda-0p9-supply: > + description: Phandle to a 0.9V regulator supply to a PHY. > + > + vdda-1p2-supply: > + description: Phandle to 1.2V regulator supply to a PHY. > + > + ports: > + $ref: /schemas/graph.yaml#/properties/ports > + > + properties: > + port@0: > + $ref: /schemas/graph.yaml#/$defs/port-base > + description: > + Sensor input. Always present. A single sensor is described by a > + single endpoint with one to four data lanes. DPHY split mode, > + where two independent sensors share the same PHY, is described > + by two endpoints; endpoint@0 with exactly two data-lanes and > + endpoint@1 with exactly one data-lane. > + unevaluatedProperties: false > + > + patternProperties: > + "^endpoint(@[0-9a-f]+)?$": endpoint suffix regexp is incorrected, this issue has been reported previously, still it is not fixed. > + $ref: /schemas/media/video-interfaces.yaml# > + unevaluatedProperties: false > + properties: > + data-lanes: > + minItems: 1 > + maxItems: 4 > + > + required: > + - data-lanes > + - remote-endpoint > + > + allOf: > + - if: > + required: > + - endpoint@1 > + then: > + properties: > + endpoint@0: > + properties: > + data-lanes: > + minItems: 2 > + maxItems: 2 > + endpoint@1: > + properties: > + data-lanes: > + maxItems: 1 > + required: > + - endpoint@0 > + > + port@1: > + $ref: /schemas/graph.yaml#/properties/port > + description: Output to the CAMSS CSID controller. > + > + required: > + - port@0 > + - port@1 > + > +required: > + - compatible > + - reg > + - "#phy-cells" > + - clocks > + - clock-names > + - interrupts > + - operating-points-v2 > + - power-domains > + - power-domain-names > + - vdda-0p9-supply > + - vdda-1p2-supply > + - ports > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + #include > + #include > + > + phy@ace4000 { > + compatible = "qcom,x1e80100-csi2-phy"; > + reg = <0x0ace4000 0x2000>; > + #phy-cells = <1>; > + > + clocks = <&camcc CAM_CC_CSIPHY0_CLK>, > + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, > + <&camcc CAM_CC_CORE_AHB_CLK>; > + clock-names = "core", > + "timer", > + "ahb"; > + > + interrupts = ; > + > + operating-points-v2 = <&csiphy_opp_table>; > + > + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>, > + <&rpmhpd RPMHPD_MMCX>, > + <&rpmhpd RPMHPD_MX>; > + power-domain-names = "top", > + "mmcx", > + "mx"; > + > + vdda-0p9-supply = <&vreg_l2c_0p9>; > + vdda-1p2-supply = <&vreg_l1c_1p2>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + csiphy0_in: endpoint { > + data-lanes = <0 1 2 3>; data-lanes values has not been corrected in accordance to linux-media requirements. > + remote-endpoint = <&sensor_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + csiphy0_out: endpoint { > + remote-endpoint = <&csid_in>; > + }; > + }; > + }; > + > + csiphy_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-300000000 { > + opp-hz = /bits/ 64 <300000000>; > + required-opps = <&rpmhpd_opp_low_svs_d1>, > + <&rpmhpd_opp_low_svs_d1>; > + }; > + }; > + }; > -- Best wishes, Vladimir