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Mon, 08 Jun 2026 06:44:50 -0700 (PDT) X-Received: by 2002:a17:902:f543:b0:2c2:27be:39a3 with SMTP id d9443c01a7336-2c227be3b4fmr113831305ad.29.1780926289645; Mon, 08 Jun 2026 06:44:49 -0700 (PDT) Received: from [10.218.33.224] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2c164f88473sm200506985ad.25.2026.06.08.06.44.44 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 08 Jun 2026 06:44:49 -0700 (PDT) Message-ID: <0ded611e-1932-470c-8e80-9a5e94268583@oss.qualcomm.com> Date: Mon, 8 Jun 2026 19:14:43 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/6] dt-bindings: iommu: arm,smmu: Document interconnects property To: Konrad Dybcio , Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org References: <20260526-smmu_interconnect_addition-v2-0-2a6d8ca30d63@oss.qualcomm.com> <20260526-smmu_interconnect_addition-v2-1-2a6d8ca30d63@oss.qualcomm.com> <1b5ef5b8-c9f2-4eea-8040-22c1d704b529@oss.qualcomm.com> Content-Language: en-US From: Bibek Kumar Patro In-Reply-To: <1b5ef5b8-c9f2-4eea-8040-22c1d704b529@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjA4MDEzMCBTYWx0ZWRfXxWIab6psCoJu FPQ5dwPseNdn7eioxXAki7a3etpOyeRUopBdrxAwtl6GbQcVkiE3myXFmCjdOToMt0+kljRTZD5 It2gCezfkerlSDhdF7iwTLuR9IuGjo0CIdQAhZW8cBTNRAXPiEK3YuD/hn00eRgX+r/N8pFbtuX gj/hJsvl5oTXJ21xYxXC6CFGHf/wCB1M1TUSWqQHi/N5vHA7NHEVdujBOsGmlYXPvXSrt5/1T0U UQJX4jMJLflQYjEDyBokWdmr9SWzDlWG8Xq5QOKOoa3uMgzLwNPMNsmqr52UFpj1BTZx9y9Ldoh irLUvNv/4/vLKgSoc7uJ0AXEXyd0wItRqzDUw30sNqU3562jZY3Uf+CJY3HTepioNINUaaGZHQX cbJgc8PSu4qA450eKaq976fZPOGRrM2ABKg8rau3fJyggPj4bZw4I0Pib4shbbwmpQ6FgpWe96K H0WlR8FIaxp0lCpsgWA== X-Authority-Analysis: v=2.4 cv=V6BNF+ni c=1 sm=1 tr=0 ts=6a26c753 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=NEAV23lmAAAA:8 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=nHMyhPlvQ-XDY_K2CzoA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-GUID: 6IamPb3Ba-AlJvHZz-53LiSyifXsHLSA X-Proofpoint-ORIG-GUID: 6IamPb3Ba-AlJvHZz-53LiSyifXsHLSA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-08_03,2026-06-05_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 adultscore=0 spamscore=0 malwarescore=0 clxscore=1015 lowpriorityscore=0 suspectscore=0 bulkscore=0 impostorscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606080130 On 6/8/2026 3:22 PM, Konrad Dybcio wrote: > On 5/26/26 4:42 PM, Bibek Kumar Patro wrote: >> Some SoC implementations require a bandwidth vote on an interconnect >> path before the SMMU register space is accessible. Add the optional >> 'interconnects' property to the binding to allow platform DT nodes >> to describe this path. >> >> Signed-off-by: Bibek Kumar Patro >> --- >> .../devicetree/bindings/iommu/arm,smmu.yaml | 27 ++++++++++++++++++++++ >> 1 file changed, 27 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml >> index 06fb5c8e7547cb7a92823adc2772b94f747376a6..3a677ff1a18fcdf5c0ca9ec8a017d41f9eb5ff09 100644 >> --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml >> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml >> @@ -243,6 +243,13 @@ properties: >> minItems: 1 >> maxItems: 3 >> >> + interconnects: >> + maxItems: 1 >> + description: >> + Interconnect path to the SMMU register space. Required on SoCs >> + where the SMMU registers are only accessible after a bandwidth >> + vote has been placed on the interconnect fabric. >> + >> nvidia,memory-controller: >> description: | >> A phandle to the memory controller on NVIDIA Tegra186 and later SoCs. >> @@ -602,6 +609,26 @@ allOf: >> clock-names: false >> clocks: false >> >> + - if: >> + properties: >> + compatible: >> + items: >> + - enum: >> + - qcom,qcs615-smmu-500 >> + - qcom,qcs8300-smmu-500 >> + - qcom,sa8775p-smmu-500 >> + - qcom,sc7280-smmu-500 > > This is a list of targets that happen to be supported by QLI.. but should > this list not contain _all_ Qualcomm SoCs, or at least a much broader range? > > Perhaps > > if: properties: compatible: contains: qcom,adreno-smmu > > ? > As of now platforms where the issues [1] getting reported are added, the list will grow. [1]: https://github.com/qualcomm-linux/kernel/issues/297 [2]: https://lore.kernel.org/all/a437f9f9-3560-40f8-85ea-35433e33c428@oss.qualcomm.com/ > Konrad