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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b976d08e6a0sm39218666b.61.2026.03.13.04.49.23 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 13 Mar 2026 04:49:25 -0700 (PDT) Message-ID: <0df69fd0-92f0-4daa-af15-56163b812741@oss.qualcomm.com> Date: Fri, 13 Mar 2026 12:49:22 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/5] irqchip/qcom-pdc: Configure PDC to pass through mode To: "Maulik Shah (mkshah)" , Dmitry Baryshkov Cc: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Gleixner , Linus Walleij , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Sneh Mankad , Stephan Gerhold , Johan Hovold References: <20260312-hamoa_pdc-v1-0-760c8593ce50@oss.qualcomm.com> <20260312-hamoa_pdc-v1-3-760c8593ce50@oss.qualcomm.com> <771a8f63-90d1-45b5-960e-342d9041fc4d@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <771a8f63-90d1-45b5-960e-342d9041fc4d@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=T6eBjvKQ c=1 sm=1 tr=0 ts=69b3f9c7 cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=bDJMtZGroyP0dw3QX1AA:9 a=QEXdDO2ut3YA:10 a=PEH46H7Ffwr30OY-TuGO:22 X-Proofpoint-ORIG-GUID: Ei_zFzJCs2WoTbAhjLO5K_i9lI9rOA-x X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzEzMDA5MyBTYWx0ZWRfX0ZumVE5gCsXv 9WYIVvLZz/5+kglw0O6eICAJra2yov4uCvuSl62WDdziQOz9cv2wP+FNtE4ueddE4yT+5HOf2vC Vvi0u8L7YpIxE5sg2gunhUhxiZSzEXBSWv/xk6FrOviBOWyaH4KiOIY7FQ8xybSDnqbaUIKZw8Y Xu4PO25F+PHcdrgX5x60oDtGUxnnJ54ckais2FW/TJyZIGVJnJk5rsaq8e3Czll8YE6/sP5JvWW O0ndCtXnB6UXff6igmi2D3Q/zvx7+cIfpYMHROE8vKY8UD9CyUNOOt7JQyVyRJVaNJbXoy2dTE+ EecFMOT+BuFhZfsMgwKgbG6bhni4lCO1LzkYpW1rUYSJumB5eZr8mLe2AyIDuJtblovDoKr+n+q V3Cev+yuXZzcy4JSwhPkt+3VzJ9yhgQCW14g+vvOullYxUv+AD94hvukmKrGWBydGfQTZLwGSTC kzO49jiyRZt/rEOOCiA== X-Proofpoint-GUID: Ei_zFzJCs2WoTbAhjLO5K_i9lI9rOA-x X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-13_02,2026-03-13_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 lowpriorityscore=0 malwarescore=0 adultscore=0 suspectscore=0 bulkscore=0 phishscore=0 impostorscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603130093 On 3/13/26 7:40 AM, Maulik Shah (mkshah) wrote: > > > On 3/13/2026 7:52 AM, Dmitry Baryshkov wrote: >> On Thu, Mar 12, 2026 at 09:26:37PM +0530, Maulik Shah wrote: [...] >>> All the SoCs so far default uses pass through mode with the exception of >> >> Is it something that must be configured by the bootloaders? > > yes, currently changing the the mode can be done from secure world either at boot > or after boot via scm write. ..which won't work on almost any X1E devices, except CRD and IOT.. >>> x1e. x1e PDC may be set to secondary controller mode for builds on CRD >>> boards whereas it may be set to pass through mode for IoT-EVK. >>> >>> There is no way to read which current mode it is set to and make PDC work >>> in respective mode as the read access is not opened up for non secure >>> world. There is though write access opened up via SCM write API to set the >>> mode. >> >> What are going to loose? The ability to latch the wakeup sources on the >> CRD? > > CXPC (SoC level low power mode) would be lost if the device can not wake up from GPIO wakeup sources. To the best of my understanding, that's only because your approach chooses to ignore supporting the secondary controller mode and force-reconfigure, since GPIO wakeup functionality is otherwise available regardless of the mode. >>> Configure PDC mode to pass through mode for all x1e based boards via SCM >>> write. >> >> Would it make sense to always use the secondary mode instead? > > No, it would not make sense to support the secondary mode in Linux. Why? [...] >>> + * - Inform TLMM to monitor GPIO IRQs (same as MPM) >>> + * - Prevent SoC low power mode (CxPC) as PDC is not >>> + * monitoring GPIO IRQs which may be needed to wake >>> + * the SoC from low power mode. >> >> This doesn't quite match the description of "latches the GPIO IRQs". > > It does, PDC would continue to still latch the GPIO IRQs (as the mode change failed) > but PDC won't forward them to parent GIC as they are masked at PDC with __pdc_mask_intr(). Can you not refrain from masking them then, and clear them upon reception, with a write to IRQ_i_CFG[IRQ_STATUS]? The HPG states that this mechanism is only engaged for GPIO IRQs and that the forwarded interrupt will be of LEVEL_HIGH type (which is what TLMM accepts anyway) FWIW, some related work: c7984dc0a2b9 ("pinctrl: qcom: Add test case for TLMM interrupt handling") Konrad