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Fri, 4 Jul 2025 13:47:15 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ThreadId: T39b5c23212bbd78d Date: Fri, 04 Jul 2025 18:46:54 +0100 From: "Jiaxun Yang" To: "Gregory CLEMENT" , "Thomas Bogendoerfer" Cc: "Vladimir Kondratiev" , =?UTF-8?Q?Th=C3=A9o_Lebrun?= , "Tawfik Bayouk" , "Thomas Petazzoni" , "linux-mips@vger.kernel.org" , linux-kernel@vger.kernel.org Message-Id: <0eaf6e01-a690-40de-b858-4e23752486b5@app.fastmail.com> In-Reply-To: <20250704-smp_calib-v2-3-bade7e9c0463@bootlin.com> References: <20250704-smp_calib-v2-0-bade7e9c0463@bootlin.com> <20250704-smp_calib-v2-3-bade7e9c0463@bootlin.com> Subject: Re: [PATCH v2 3/3] MIPS: CPS: Optimise delay CPU calibration for SMP Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable =E5=9C=A82025=E5=B9=B47=E6=9C=884=E6=97=A5=E5=91=A8=E4=BA=94 =E4=B8=8B=E5= =8D=884:13=EF=BC=8CGregory CLEMENT=E5=86=99=E9=81=93=EF=BC=9A > On MIPS architecture with CPS-based SMP support, all CPU cores in the > same cluster run at the same frequency since they share the same L2 > cache, requiring a fixed CPU/L2 cache ratio. > > This allows to implement calibrate_delay_is_known(), which will return > 0 (triggering calibration) only for the primary CPU of each > cluster. For other CPUs, we can simply reuse the value from their > cluster's primary CPU core. > > With the introduction of this patch, a configuration running 32 cores > spread across two clusters sees a significant reduction in boot time > by approximately 600 milliseconds. > > Signed-off-by: Gregory CLEMENT Reviewed-by: Jiaxun Yang Thanks! --=20 - Jiaxun