From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-m3271.qiye.163.com (mail-m3271.qiye.163.com [220.197.32.71]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EF72F22D7A9 for ; Fri, 10 Apr 2026 01:02:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.32.71 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775782924; cv=none; b=qGFJ0/+uoYoHngxmNVG/SfnuVDWoAA9U0oh1U2ifs5pocWQfSSP7PoKnom5NhDpHOmycP9fOMcRS1UyXJkvypb6owpmZHJZEFLXb573XFXE7CBA8bbFjvEhQQuRwlo+706n1iV/7YSzSUbDrGiSJNCZcfDDCGLotA+AOINJqg0U= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775782924; c=relaxed/simple; bh=A0ONo3xXGMXAQpPVoi5srZ+FyKvjT4aBhG93JNBRBQU=; h=Message-ID:Date:MIME-Version:Cc:Subject:To:References:From: In-Reply-To:Content-Type; b=eY92qNH0ez3tSeMSZ2MjucDGcptNaHA6JY+JWfBVJyQ8nWr8b4Y04pG3vopOusGPqiVCnX/oMzj4MCQmEwHMIFAJ8HC9QeSn6aEXYzjdQSBNTOaq1AsqXfyeTNKVsB25bfNgUUnQjPbHNazDkvBocttEtzhNh1Tm6lnthsTON+w= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=KevY7tvx; arc=none smtp.client-ip=220.197.32.71 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="KevY7tvx" Received: from [172.16.12.17] (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 3a2aff74f; Fri, 10 Apr 2026 08:46:33 +0800 (GMT+08:00) Message-ID: <0ee54525-928e-a1ce-ec2d-1f85cf15abbc@rock-chips.com> Date: Fri, 10 Apr 2026 08:46:29 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.13.1 Cc: shawn.lin@rock-chips.com, Niklas Cassel Subject: Re: [PATCH v1] phy: rockchip-snps-pcie3:phy: Configure clkreq_n and PowerDown for all lanes To: Anand Moon , Vinod Koul , Neil Armstrong , Heiko Stuebner , "open list:GENERIC PHY FRAMEWORK" , "moderated list:ARM/Rockchip SoC support" , "open list:ARM/Rockchip SoC support" , open list References: <20260409044939.7647-1-linux.amoon@gmail.com> From: Shawn Lin In-Reply-To: <20260409044939.7647-1-linux.amoon@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-HM-Tid: 0a9d74dadb4909cckunmd6738a1c517e0a X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZGUhISlYeT09DSh9IHUlMSRlWFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0 hVSktLVUpCS0tZBg++ DKIM-Signature: a=rsa-sha256; b=KevY7tvxQt/iVUsWMn2Prf/um0QObBwPIG7Q9aew+klGem7Dz27DWVmhx+CBl/EylsycsAXfC4rFvkTqD+/55YcuWrDVdPkiLqt6/J4AM4vh8vie2nMl48wf+EAATzVK8etESyy8qY5Ri3Fe3hz3yPAfTKjaNi7KDfWYyGB1ZE0=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=Mqjz6IXi2Nh7CDAEaokpRybVDDSN/VvLWMpvHJGfmOg=; h=date:mime-version:subject:message-id:from; Hi Anand 在 2026/04/09 星期四 12:49, Anand Moon 写道: > During the rk3588_p3phy_init sequence, the driver now explicitly > configures each lane's CON0 register to ensure > - PIPE 4.3 Compliance: clkreq_n (bit 6) is forced low (asserted) to meet > sideband signal requirements. clkreq_n is now force asserted via controller driver if supports_clkreq is not set. > - Active Power State: PowerDown[3:0] (bits 11:8) is set to P0 > (Normal Operational State) to ensure the PHY is fully powered and ready > for link training. > P0 is the nature state when linking up. I don't know why it should be P0 before we even don't know whether the device is present. > These changes ensure that all lanes are consistently transitioned from > reset into a known-good operational state, preventing undefined behavior > and ensuring the PHY is ready for high-speed data transmission. > > Cc: Niklas Cassel > Signed-off-by: Anand Moon > --- > .../phy/rockchip/phy-rockchip-snps-pcie3.c | 28 +++++++++++++++++-- > 1 file changed, 26 insertions(+), 2 deletions(-) > > diff --git a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c > index 4e8ffd173096..f46e13e79a0e 100644 > --- a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c > +++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c > @@ -7,6 +7,7 @@ > > #include > #include > +#include > #include > #include > #include > @@ -35,10 +36,14 @@ > #define RK3588_PCIE3PHY_GRF_CMN_CON0 0x0 > #define RK3588_PCIE3PHY_GRF_PHY0_STATUS1 0x904 > #define RK3588_PCIE3PHY_GRF_PHY1_STATUS1 0xa04 > +#define RK3588_PCIE3PHY_GRF_PHY0_LN0_CON0 0x1000 > #define RK3588_PCIE3PHY_GRF_PHY0_LN0_CON1 0x1004 > #define RK3588_PCIE3PHY_GRF_PHY0_LN1_CON1 0x1104 > +#define RK3588_PCIE3PHY_GRF_PHY0_LN1_CON0 0x1100 > +#define RK3588_PCIE3PHY_GRF_PHY1_LN0_CON0 0x2000 > #define RK3588_PCIE3PHY_GRF_PHY1_LN0_CON1 0x2004 > #define RK3588_PCIE3PHY_GRF_PHY1_LN1_CON1 0x2104 > +#define RK3588_PCIE3PHY_GRF_PHY1_LN1_CON0 0x2100 > #define RK3588_SRAM_INIT_DONE(reg) (reg & BIT(0)) > > #define RK3588_BIFURCATION_LANE_0_1 BIT(0) > @@ -49,6 +54,13 @@ > #define RK3588_PCIE1LN_SEL_EN (GENMASK(1, 0) << 16) > #define RK3588_PCIE30_PHY_MODE_EN (GENMASK(2, 0) << 16) > > +static const u32 rk3588_lane_con0[] = { > + RK3588_PCIE3PHY_GRF_PHY0_LN0_CON0, > + RK3588_PCIE3PHY_GRF_PHY0_LN1_CON0, > + RK3588_PCIE3PHY_GRF_PHY1_LN0_CON0, > + RK3588_PCIE3PHY_GRF_PHY1_LN1_CON0, > +}; > + > struct rockchip_p3phy_ops; > > struct rockchip_p3phy_priv { > @@ -142,7 +154,7 @@ static int rockchip_p3phy_rk3588_init(struct rockchip_p3phy_priv *priv) > { > u32 reg = 0; > u8 mode = RK3588_LANE_AGGREGATION; /* default */ > - int ret; > + int ret, i; > > regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_PHY0_LN0_CON1, > priv->rx_cmn_refclk_mode[0] ? RK3588_RX_CMN_REFCLK_MODE_EN : > @@ -161,7 +173,7 @@ static int rockchip_p3phy_rk3588_init(struct rockchip_p3phy_priv *priv) > regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, BIT(8) | BIT(24)); > > /* Set bifurcation if needed */ > - for (int i = 0; i < priv->num_lanes; i++) { > + for (i = 0; i < priv->num_lanes; i++) { > if (priv->lanes[i] > 1) > mode &= ~RK3588_LANE_AGGREGATION; > if (priv->lanes[i] == 3) > @@ -174,6 +186,18 @@ static int rockchip_p3phy_rk3588_init(struct rockchip_p3phy_priv *priv) > regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, > RK3588_PCIE30_PHY_MODE_EN | reg); > > + for (i = 0; i < priv->num_lanes && i < ARRAY_SIZE(rk3588_lane_con0); i++) { > + u32 base = rk3588_lane_con0[i]; > + > + /* clkreq_n = 0 (asserted low for PIPE 4.3) */ > + regmap_write(priv->phy_grf, base, > + FIELD_PREP_WM16(BIT(6), 0)); > + > + /* PowerDown = P0 (0x0, fully active) */ > + regmap_write(priv->phy_grf, base, > + FIELD_PREP_WM16(GENMASK(11, 8), 0x0)); > + } > + > /* Set pcie1ln_sel in PHP_GRF_PCIESEL_CON */ > if (!IS_ERR(priv->pipe_grf)) { > reg = mode & (RK3588_BIFURCATION_LANE_0_1 | RK3588_BIFURCATION_LANE_2_3); > > base-commit: 7f87a5ea75f011d2c9bc8ac0167e5e2d1adb1594