From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: Kuogee Hsieh <quic_khsieh@quicinc.com>,
dri-devel@lists.freedesktop.org, robdclark@gmail.com,
sean@poorly.run, swboyd@chromium.org, dianders@chromium.org,
vkoul@kernel.org, daniel@ffwll.ch, airlied@linux.ie,
agross@kernel.org, bjorn.andersson@linaro.org
Cc: quic_abhinavk@quicinc.com, quic_sbillaka@quicinc.com,
freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v5 1/3] drm/msm/dp: cleared DP_DOWNSPREAD_CTRL register before start link training
Date: Mon, 12 Sep 2022 21:39:52 +0300 [thread overview]
Message-ID: <0f381285-860f-aaa2-2ae7-834608d0b4e8@linaro.org> (raw)
In-Reply-To: <1662999830-13916-2-git-send-email-quic_khsieh@quicinc.com>
On 12/09/2022 19:23, Kuogee Hsieh wrote:
> DOWNSPREAD_CTRL (0x107) shall be cleared to 0 upon power-on reset or an
> upstream device disconnect. This patch will enforce this rule by always
> cleared DOWNSPREAD_CTRL register to 0 before start link training. At rare
> case that DP MSA timing parameters may be mis-interpreted by the sink
> which causes audio sampling rate be calculated wrongly and cause audio
> did not work at sink if DOWNSPREAD_CTRL register is not cleared to 0.
>
> Changes in v2:
> 1) fix spelling at commit text
> 2) merge ssc variable into encoding[0]
>
> Changes in v3:
> -- correct spelling of DOWNSPREAD_CTRL
> -- replace err with len of ssize_t
>
> Changes in v4:
> -- split into 2 patches
>
> Fixes: 154b5a7da0fd ("drm/msm/dp: add displayPort driver support")
> Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
> ---
> drivers/gpu/drm/msm/dp/dp_ctrl.c | 13 +++++--------
> 1 file changed, 5 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c
> index ab6aa13..2c74c59 100644
> --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c
> +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c
> @@ -1245,8 +1245,7 @@ static int dp_ctrl_link_train(struct dp_ctrl_private *ctrl,
> {
> int ret = 0;
> const u8 *dpcd = ctrl->panel->dpcd;
> - u8 encoding = DP_SET_ANSI_8B10B;
> - u8 ssc;
> + u8 encoding[] = { 0, DP_SET_ANSI_8B10B };
> u8 assr;
> struct dp_link_info link_info = {0};
>
> @@ -1258,13 +1257,11 @@ static int dp_ctrl_link_train(struct dp_ctrl_private *ctrl,
>
> dp_aux_link_configure(ctrl->aux, &link_info);
>
> - if (drm_dp_max_downspread(dpcd)) {
> - ssc = DP_SPREAD_AMP_0_5;
> - drm_dp_dpcd_write(ctrl->aux, DP_DOWNSPREAD_CTRL, &ssc, 1);
> - }
> + if (drm_dp_max_downspread(dpcd))
> + encoding[0] |= DP_SPREAD_AMP_0_5;
It would be simpler to call drm_dp_dpcd_write(ssc, DP_DOWNSPREAD_CTRL,
1) unconditionally here. You won't have to change the
encoding/DP_MAIN_LINK_CHANNEL_CODING_SET/etc.
>
> - drm_dp_dpcd_write(ctrl->aux, DP_MAIN_LINK_CHANNEL_CODING_SET,
> - &encoding, 1);
> + /* config DOWNSPREAD_CTRL and MAIN_LINK_CHANNEL_CODING_SET */
> + drm_dp_dpcd_write(ctrl->aux, DP_DOWNSPREAD_CTRL, encoding, 2);
>
> if (drm_dp_alternate_scrambler_reset_cap(dpcd)) {
> assr = DP_ALTERNATE_SCRAMBLER_RESET_ENABLE;
--
With best wishes
Dmitry
next prev parent reply other threads:[~2022-09-12 18:41 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-12 16:23 [PATCH v5 0/3] cleared DP_DOWNSPREAD_CTRL register Kuogee Hsieh
2022-09-12 16:23 ` [PATCH v5 1/3] drm/msm/dp: cleared DP_DOWNSPREAD_CTRL register before start link training Kuogee Hsieh
2022-09-12 18:39 ` Dmitry Baryshkov [this message]
2022-09-12 19:21 ` Kuogee Hsieh
2022-09-12 19:25 ` Dmitry Baryshkov
2022-09-30 1:36 ` Abhinav Kumar
2022-09-12 16:23 ` [PATCH v5 2/3] drm/msm/dp: replace variable err with len at dp_aux_link_power_up() Kuogee Hsieh
2022-09-12 18:34 ` Dmitry Baryshkov
2022-09-12 16:23 ` [PATCH v5 3/3] drm/msm/dp: retry 3 times if set sink to D0 poweer state failed Kuogee Hsieh
2022-09-12 18:37 ` Dmitry Baryshkov
2022-09-12 19:26 ` Kuogee Hsieh
2022-11-02 15:51 ` Dmitry Baryshkov
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