Re: [PATCH 2/2] arm64: dts: ti: k3-am65: Add OSPI DT node

[Vignesh Raghavendra <vigneshr@ti.com>]

Hi,

On 10/12/19 3:06 pm, Vignesh Raghavendra wrote:
> AM654 SoC has two Cadence OSPI controller instances under Flash
> subsystem (FSS). Add DT nodes for the same.
> 


Please ignore this patch... I missed to update Device IDs, will post a
v2. Sorry for the noise

Regards
Vignesh


> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
> ---
>  arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi       | 38 +++++++++++++++++++
>  arch/arm64/boot/dts/ti/k3-am65.dtsi           | 11 +++++-
>  .../arm64/boot/dts/ti/k3-am654-base-board.dts | 36 ++++++++++++++++++
>  3 files changed, 83 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
> index 7bdf5342f58f..aec720f35578 100644
> --- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
> @@ -95,4 +95,42 @@ adc {
>  			compatible = "ti,am654-adc", "ti,am3359-adc";
>  		};
>  	};
> +
> +	fss: fss@47000000 {
> +		compatible = "simple-bus";
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +
> +		ospi0: spi@47040000 {
> +			compatible = "ti,am654-ospi", "cdns,qspi-nor";
> +			reg = <0x0 0x47040000 0x0 0x100>,
> +				<0x5 0x00000000 0x1 0x0000000>;
> +			interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>;
> +			cdns,fifo-depth = <256>;
> +			cdns,fifo-width = <4>;
> +			cdns,trigger-address = <0x50000000>;
> +			clocks = <&k3_clks 55 5>;
> +			assigned-clocks = <&k3_clks 55 5>;
> +			assigned-clock-parents = <&k3_clks 55 7>;
> +			assigned-clock-rates = <166666666>;
> +			power-domains = <&k3_pds 55 TI_SCI_PD_EXCLUSIVE>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		ospi1: spi@47050000 {
> +			compatible = "ti,am654-ospi", "cdns,qspi-nor";
> +			reg = <0x0 0x47050000 0x0 0x100>,
> +				<0x7 0x00000000 0x1 0x00000000>;
> +			interrupts = <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>;
> +			cdns,fifo-depth = <256>;
> +			cdns,fifo-width = <4>;
> +			cdns,trigger-address = <0x58000000>;
> +			clocks = <&k3_clks 55 16>;
> +			power-domains = <&k3_pds 55 TI_SCI_PD_EXCLUSIVE>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +	};
>  };
> diff --git a/arch/arm64/boot/dts/ti/k3-am65.dtsi b/arch/arm64/boot/dts/ti/k3-am65.dtsi
> index 6dfccd5d56c8..d38720bc2551 100644
> --- a/arch/arm64/boot/dts/ti/k3-am65.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am65.dtsi
> @@ -80,7 +80,11 @@ cbass_main: interconnect@100000 {
>  			 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
>  			 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
>  			 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
> -			 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>;
> +			 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
> +			 <0x00 0x50000000 0x00 0x50000000 0x00 0x8000000>,
> +			 <0x00 0x70000000 0x00 0x70000000 0x00 0x200000>,
> +			 <0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>,
> +			 <0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>;
>  
>  		cbass_mcu: interconnect@28380000 {
>  			compatible = "simple-bus";
> @@ -94,7 +98,10 @@ cbass_mcu: interconnect@28380000 {
>  				 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP */
>  				 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
>  				 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
> -				 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>; /* OSPI space 1 */
> +				 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI space 1 */
> +				 <0x00 0x50000000 0x00 0x50000000 0x00 0x8000000>, /*  FSS OSPI0 data region 1 */
> +				 <0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>, /* FSS OSPI0 data region 3*/
> +				 <0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>; /* FSS OSPI1 data region 3*/
>  
>  			cbass_wakeup: interconnect@42040000 {
>  				compatible = "simple-bus";
> diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
> index 8a85b482ad31..94bec7aa9baf 100644
> --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
> +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
> @@ -69,6 +69,22 @@ AM65X_WKUP_IOPAD(0x0030, PIN_INPUT, 7) /* (R5) WKUP_GPIO0_24 */
>  			AM65X_WKUP_IOPAD(0x003c, PIN_INPUT, 7) /* (P2) WKUP_GPIO0_27 */
>  		>;
>  	};
> +
> +	mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins_default {
> +		pinctrl-single,pins = <
> +			AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* (V1) MCU_OSPI0_CLK */
> +			AM65X_WKUP_IOPAD(0x0008, PIN_INPUT, 0)	 /* (U2) MCU_OSPI0_DQS */
> +			AM65X_WKUP_IOPAD(0x000c, PIN_INPUT, 0)  /* (U4) MCU_OSPI0_D0 */
> +			AM65X_WKUP_IOPAD(0x0010, PIN_INPUT, 0)  /* (U5) MCU_OSPI0_D1 */
> +			AM65X_WKUP_IOPAD(0x0014, PIN_INPUT, 0)  /* (T2) MCU_OSPI0_D2 */
> +			AM65X_WKUP_IOPAD(0x0018, PIN_INPUT, 0)  /* (T3) MCU_OSPI0_D3 */
> +			AM65X_WKUP_IOPAD(0x001c, PIN_INPUT, 0)  /* (T4) MCU_OSPI0_D4 */
> +			AM65X_WKUP_IOPAD(0x0020, PIN_INPUT, 0)  /* (T5) MCU_OSPI0_D5 */
> +			AM65X_WKUP_IOPAD(0x0024, PIN_INPUT, 0)  /* (R2) MCU_OSPI0_D6 */
> +			AM65X_WKUP_IOPAD(0x0028, PIN_INPUT, 0)  /* (R3) MCU_OSPI0_D7 */
> +			AM65X_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* (R4) MCU_OSPI0_CSn0 */
> +		>;
> +	};
>  };
>  
>  &main_pmx0 {
> @@ -339,3 +355,23 @@ &mailbox0_cluster10 {
>  &mailbox0_cluster11 {
>  	status = "disabled";
>  };
> +
> +&ospi0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
> +
> +	flash@0{
> +		compatible = "jedec,spi-nor";
> +		reg = <0x0>;
> +		spi-tx-bus-width = <1>;
> +		spi-rx-bus-width = <8>;
> +		spi-max-frequency = <40000000>;
> +		cdns,tshsl-ns = <60>;
> +		cdns,tsd2d-ns = <60>;
> +		cdns,tchsh-ns = <60>;
> +		cdns,tslch-ns = <60>;
> +		cdns,read-delay = <0>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +	};
> +};
> 

-- 
Regards
Vignesh