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Sun, 28 Jun 2026 23:53:41 -0700 (PDT) X-Received: by 2002:a17:90b:558f:b0:37f:be6c:f3f2 with SMTP id 98e67ed59e1d1-37fbe6cf68emr5802847a91.2.1782716021018; Sun, 28 Jun 2026 23:53:41 -0700 (PDT) Received: from [10.204.78.62] ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3801dcf2196sm289571a91.1.2026.06.28.23.53.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 28 Jun 2026 23:53:40 -0700 (PDT) Message-ID: <0f3a199a-d9b7-4d8b-a17a-85146c618977@oss.qualcomm.com> Date: Mon, 29 Jun 2026 12:23:35 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 3/3] arm64: dts: qcom: kodiak: Set up 4-lane DP To: Dmitry Baryshkov , Bjorn Andersson Cc: Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Mahadevan P References: <20260429-kodiak_v2-v2-0-c3a703cc30eb@oss.qualcomm.com> <20260429-kodiak_v2-v2-3-c3a703cc30eb@oss.qualcomm.com> Content-Language: en-US From: Mahadevan P In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjI5MDA1NyBTYWx0ZWRfXx4q8ndvguYEl yss6wd6y2g2EupEs8II+OedN0OTe3xy10H5wtxBAeis9+tXtV2V009XMUWIr11dtAumTMLt0Uy4 l2mjdoa8pG984G83gXYf5Fqsw1Ke2SzDJmYrW8e9d5P0OOkaO819DZwkvGJ+X2kJBI91Fw38ubQ 16nx7WUoMeoAWOfIIVzvc4ZW35/h6SH6DudqtnoH42eobmhx5iS9svXpkgy/GGm6y9cNrzuL6LT 8gHWu+tlAgmBMDXKbb1JuysablVpwHZnH5Y4vbi/k9wgWwQ3pEtuj+YecSov37sDijaF9lQy2ki 8srmBUtIw38F4L4VunKEtAO8hV/vTIo/5cz/4QvfOuSc0rNAZ76gTFDs2sK14aZV0ppSfjHwDM7 TU2XQ5yjQI+Y0+rimxur0YI3Xm9hx1F8Z4wVEymT/cjMb2Ms9fIyD4GDeaSgumzLlPbjDZxOad5 FwApH9ZyiO2fwEFt6iw== X-Proofpoint-GUID: iGE0xfEScVTtOMS3WQRMmkO6K0WpuZMC X-Proofpoint-Spam-Info: AW1haW4tMjYwNjI5MDA1NyBTYWx0ZWRfX7h2Hma1kIHZW 75lQVXXr+Ki9veZjcTz+UMwRSD06ioWXnZGVaofuyW3uXsCdI2v4FAeONzOa2GVtt1wi2F42EoA 0BdRGvYK9AXbwmJrO8cZxRoTwds2rRA= X-Proofpoint-ORIG-GUID: iGE0xfEScVTtOMS3WQRMmkO6K0WpuZMC X-Authority-Analysis: v=2.4 cv=BdnoFLt2 c=1 sm=1 tr=0 ts=6a421676 cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=4MOLs5CX9ZFlVaH_dukA:9 a=QEXdDO2ut3YA:10 a=x9snwWr2DeNwDh03kgHS:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-29_02,2026-06-26_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 clxscore=1015 suspectscore=0 bulkscore=0 impostorscore=0 spamscore=0 lowpriorityscore=0 adultscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2606290057 On 6/28/2026 5:51 PM, Dmitry Baryshkov wrote: > On Sat, Jun 27, 2026 at 09:28:47PM -0500, Bjorn Andersson wrote: >> On Wed, Apr 29, 2026 at 12:10:42PM +0530, Mahadevan P wrote: >>> From: Mahadevan P >>> >>> Allow up to 4 lanes for the DisplayPort link from the PHY to the >> >> It's hard to follow your thought process here, as you didn't document >> why this change should be made. Start your commit message by describing >> the problem that your change is solving. >> >>> controller now the mode-switch events can reach the QMP Combo PHY. >>> >>> Signed-off-by: Mahadevan P >>> --- >>> arch/arm64/boot/dts/qcom/kodiak.dtsi | 2 +- >>> 1 file changed, 1 insertion(+), 1 deletion(-) >>> >>> diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi >>> index 0acc6917d7aa..204513a6bd89 100644 >>> --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi >>> +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi >>> @@ -5704,7 +5704,7 @@ dp_in: endpoint { >>> port@1 { >>> reg = <1>; >>> mdss_dp_out: endpoint { >>> - data-lanes = <0 1>; >>> + data-lanes = <0 1 2 3>; >> >> And as Dmitry pointed out, not all Kodiak-based boards have 4 DP-lanes >> wired up. > > As a bit of explanation and context for Mahadevan. The link between DP > controller and PHY is 4 lanes. Historically we have been declaring two > lanes here because the DP / USB <-> PHY interaction wasn't finalzied, > so it was not possible to use 4 lanes for DP. The issue was solved and > now most of the platforms should be able to have all 4 lanes here. > However in some cases, platforms like Herobrine use this as a quirk, > because it was impossible to describe various quirks that they have > implemented (in case of Herobrine it is a fancy 2 lane split / mux). > > I'd recommend the following approach: enable 4 lanes in the kodiak.dtsi, > while, at the same time, leaving 2 lanes for the following boards (which > should keep the board-specific override for now): > - sc7280-herobrine.dtsi, it requires special handling for 2-lanes > topology > - qcm6490-particle-tachyon.dts, it might be missing a redriver > - qcs6490-thundercomm-rubikpi3.dts, it might be missing a redriver > > The Tachyon and Rubik Pi 3 boards might be missing a redriver, which > would need a reprogramming to support proper 4 lanes DP (or they don't). > Anyway, that needs to be confirmed by somebody having the schematics. > Thanks, for conclusion on this, i will update the changes validate and repost. Thanks, Mahadevan