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Thu, 10 Apr 2025 13:08:07 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 53AD86rA014610 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 10 Apr 2025 13:08:06 GMT Received: from [10.216.14.182] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 10 Apr 2025 06:07:57 -0700 Message-ID: <0f4eca6c-67df-4730-88b3-a277903deabc@quicinc.com> Date: Thu, 10 Apr 2025 18:37:54 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 07/10] arm64: dts: qcom: sa8775p-ride: add anx7625 DSI to DP bridge nodes To: Dmitry Baryshkov , CC: , , , , , , , , , , , , , , , , , , , , , , , , References: <20250404115539.1151201-1-quic_amakhija@quicinc.com> <20250404115539.1151201-8-quic_amakhija@quicinc.com> Content-Language: en-US From: Ayushi Makhija In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: u6cLcpuCQZXqIApBuHPMYAggNJBvecAZ X-Authority-Analysis: v=2.4 cv=LLlmQIW9 c=1 sm=1 tr=0 ts=67f7c2b7 cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=COk6AnOGAAAA:8 a=zjBtcsmdu44VOzoy24MA:9 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: u6cLcpuCQZXqIApBuHPMYAggNJBvecAZ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-10_03,2025-04-08_04,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 bulkscore=0 clxscore=1015 mlxlogscore=999 malwarescore=0 phishscore=0 lowpriorityscore=0 priorityscore=1501 mlxscore=0 spamscore=0 adultscore=0 suspectscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504100095 Hi Dmirity/Konard On 4/7/2025 1:42 AM, Dmitry Baryshkov wrote: > On Fri, Apr 04, 2025 at 05:25:36PM +0530, Ayushi Makhija wrote: >> Add anx7625 DSI to DP bridge device nodes. >> >> Signed-off-by: Ayushi Makhija >> --- >> arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi | 208 ++++++++++++++++++++- >> 1 file changed, 207 insertions(+), 1 deletion(-) >> >> diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi b/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi >> index 175f8b1e3b2d..8e784ccf4138 100644 >> --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi >> @@ -28,6 +28,13 @@ chosen { >> stdout-path = "serial0:115200n8"; >> }; >> >> + vph_pwr: vph-pwr-regulator { >> + compatible = "regulator-fixed"; >> + regulator-name = "vph_pwr"; >> + regulator-always-on; >> + regulator-boot-on; >> + }; >> + >> vreg_conn_1p8: vreg_conn_1p8 { >> compatible = "regulator-fixed"; >> regulator-name = "vreg_conn_1p8"; >> @@ -128,6 +135,30 @@ dp1_connector_in: endpoint { >> }; >> }; >> }; >> + >> + dp-dsi0-connector { >> + compatible = "dp-connector"; >> + label = "DSI0"; >> + type = "full-size"; >> + >> + port { >> + dp_dsi0_connector_in: endpoint { >> + remote-endpoint = <&dsi2dp_bridge0_out>; >> + }; >> + }; >> + }; >> + >> + dp-dsi1-connector { >> + compatible = "dp-connector"; >> + label = "DSI1"; >> + type = "full-size"; >> + >> + port { >> + dp_dsi1_connector_in: endpoint { >> + remote-endpoint = <&dsi2dp_bridge1_out>; >> + }; >> + }; >> + }; >> }; >> >> &apps_rsc { >> @@ -517,9 +548,135 @@ &i2c11 { >> >> &i2c18 { >> clock-frequency = <400000>; >> - pinctrl-0 = <&qup_i2c18_default>; >> + pinctrl-0 = <&qup_i2c18_default>, >> + <&io_expander_intr_active>, >> + <&io_expander_reset_active>; > > These pinctrl entries should go to the IO expander itself. > >> pinctrl-names = "default"; >> + >> status = "okay"; >> + >> + io_expander: gpio@74 { >> + compatible = "ti,tca9539"; >> + reg = <0x74>; >> + interrupts-extended = <&tlmm 98 IRQ_TYPE_EDGE_BOTH>; >> + gpio-controller; >> + #gpio-cells = <2>; >> + interrupt-controller; >> + #interrupt-cells = <2>; >> + >> + gpio2-hog { > > This needs a huuge explanation in the commit message. Otherwise I'd say > these pins should likely be used by the corresponding anx bridges. Thanks, for the review. Previously, I was referring to the downstream DT and misunderstood the use of gpio-hog. After reading the schematic, I realized that gpio2, gpio3, gpio10, and gpio11 are all input pins to the IO expander TC9539. We have already configured gpio2 and gpio10 as interrupts in the ANX7625 bridges, so the gpio-hog is not required. It is working without the gpio-hog configuration. Thanks, Ayushi