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Tue, 18 Feb 2025 02:05:53 -0800 (PST) Message-ID: <0f6369fd-3236-40eb-bf8f-3c3d675137c9@linaro.org> Date: Tue, 18 Feb 2025 10:05:48 +0000 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v12 0/7] Coresight: Add Coresight TMC Control Unit driver To: Jie Gan , Suzuki K Poulose Cc: Tingwei Zhang , Jinlong Mao , coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, Mike Leach , Alexander Shishkin , Maxime Coquelin , Alexandre Torgue , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio References: <20250217093024.1133096-1-quic_jiegan@quicinc.com> Content-Language: en-US From: James Clark In-Reply-To: <20250217093024.1133096-1-quic_jiegan@quicinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 17/02/2025 9:30 am, Jie Gan wrote: > From: Jie Gan > > The Coresight TMC Control Unit(CTCU) device hosts miscellaneous configuration > registers to control various features related to TMC ETR device. > > The CTCU device works as a helper device physically connected to the TMC ETR device. > --------------------------------------------------------- > |ETR0| |ETR1| > . \ / . > . \ / . > . \ / . > . \ / . > --------------------------------------------------- > ETR0ATID0-ETR0ATID3 CTCU ETR1ATID0-ETR1ATID3 > --------------------------------------------------- > Each ETR has four ATID registers with 128 bits long in total. > e.g. ETR0ATID0-ETR0ATID3 registers are used by ETR0 device. > > Based on the trace id which is programed in CTCU ATID register of > specific ETR, trace data with that trace id can get into ETR's buffer > while other trace data gets ignored. The number of CTCU ATID registers > depends on the number of defined TMC ETR devices. For example, two TMC > ETR devices need eight ATID registers. ETR0 with ETR0ATID0-ETR0ATID3 > and ETR1 with ETR1ATID0-ETRATID3. > > The significant challenge in enabling the data filter function is how > to collect the trace ID of the source device. The introduction of > trace_id callback function addresses this challenge. The callback function > collects trace ID of the device and return it back. The trace ID will be > stored in the structure called coresight_path and transmitted to helper > and sink devices. > > The coresight_path structure is created to address how to transmit > parameters needs by coresight_enable_path/coresight_disbale_path > functions. > > Here is the definition of the struct coresight_path: > /** > * struct coresight_path - data needed by enable/disable path > * @path: path from source to sink. > * @trace_id: trace_id of the whole path. > */ > struct coresight_path { > struct list_head *path; > u8 trace_id; > }; > > The atid_offset mentioned before is the offset to ATID register in CTCU > device. > > Enabling the source device will configure one bit in the ATID register based > on its trace ID. > Disabling the source devices will reset the bit in the AITD register > based on its trace ID. > > Useage: > Enable: > STM device with trace ID 5 and ETR0 is activated. > Bitmap before the enablement: > ETR0ATID0: > 31..................543210 > ========================== > 0000000000000000000000...0 > ========================== > > Bitmap after the enablement: > 31..................543210 > ========================== > 0000000000000...0000100000 > ========================== > > The bit 5 of the ETR0ATID0 register is configured to 1 when enabling the > STM device. > > Disable: > STM device with trace ID 5 and ETR0 is activated. > Bitmap before the disablement: > ETR0ATID0: > 31................6543210 > ========================= > 000000000010111...0100000 > ========================= > > Bitmap after the disablement > ETR0ATID0: > 31................6543210 > ========================= > 000000000010111...0000000 > ========================= > > The bit 5 of the ETR0ATID0 register is reset to 0 when disabling the STM > device. > > Sincere thanks to James Clark for providing an excellent idea to handle > the trace_id of the path. > > Changes in V12: > 1. Update the method for allocating trace_id for perf mode. > Link to V11 - https://lore.kernel.org/linux-arm-msm/20250214024021.249655-1-quic_jiegan@quicinc.com/ > I tested the latest change, looks good to me.