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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by BL6PEPF00020E65.mail.protection.outlook.com (10.167.249.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9745.21 via Frontend Transport; Mon, 30 Mar 2026 22:26:17 +0000 Received: from nigeria-2635-os.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Mon, 30 Mar 2026 17:26:16 -0500 From: Ashish Kalra To: , , , , , , , , , , , CC: , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 2/6] x86/sev: Add support for enabling RMPOPT Date: Mon, 30 Mar 2026 22:26:06 +0000 Message-ID: <0f6539b8fd4c4e7d40fb19e6b3255a120664bfb4.1774755884.git.ashish.kalra@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: satlexmb08.amd.com (10.181.42.217) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF00020E65:EE_|CH3PR12MB9100:EE_ X-MS-Office365-Filtering-Correlation-Id: d76f86e4-6df3-426e-3dc8-08de8eab5c98 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700016|7416014|376014|22082099003|18002099003|56012099003|921020; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Sq8ksmTVA37FZpv92TM+Wv0QPLY3x4V2B7N4toQhUtK7w9KhaHPlreFT8Mts4GS/ekyDklRoNJ4TgfV/rO4GRqKWVTEt+HFzlpDuDPQncMKSluS1tpu0gYA0yjhUjMLFk5KN3+akCSF7HtDkC+sFzzMJUw0B12CvXG1Bo+M3C493+QKulhCA6/d1qVUM3+joI032jwPknscASDbp6anGJixerBBX0ROa4ZZkqk6pF3FhiDgUcICOcjCJC3bAQL9TNzSbHpSmJJDJHv+i/FwM7KxBDHDMleB26pR6W56KWIxyrJZE4NWNR7D34Ui6fUwdNFQ7I9liyXoez8+QTEQYGgSgUr3QDUKik5pRMtP+aI8dn1kqyu5kpeGjC0Asox/WOdgs19qhwp+aVJHPaTuFYxS67A3RZ0SZNfhsbaWdUCp4g5cCPZnEQnNwyT6/u6Hp X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Mar 2026 22:26:17.6784 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d76f86e4-6df3-426e-3dc8-08de8eab5c98 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00020E65.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9100 From: Ashish Kalra The new RMPOPT instruction helps manage per-CPU RMP optimization structures inside the CPU. It takes a 1GB-aligned physical address and either returns the status of the optimizations or tries to enable the optimizations. Per-CPU RMPOPT tables support at most 2 TB of addressable memory for RMP optimizations. Initialize the per-CPU RMPOPT table base to the starting physical address. This enables RMP optimization for up to 2 TB of system RAM on all CPUs. Suggested-by: Thomas Lendacky Suggested-by: Dave Hansen Signed-off-by: Ashish Kalra --- arch/x86/include/asm/msr-index.h | 3 +++ arch/x86/virt/svm/sev.c | 26 ++++++++++++++++++++++++++ 2 files changed, 29 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index be3e3cc963b2..9c8a6dfd7891 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -758,6 +758,9 @@ #define MSR_AMD64_SEG_RMP_ENABLED_BIT 0 #define MSR_AMD64_SEG_RMP_ENABLED BIT_ULL(MSR_AMD64_SEG_RMP_ENABLED_BIT) #define MSR_AMD64_RMP_SEGMENT_SHIFT(x) (((x) & GENMASK_ULL(13, 8)) >> 8) +#define MSR_AMD64_RMPOPT_BASE 0xc0010139 +#define MSR_AMD64_RMPOPT_ENABLE_BIT 0 +#define MSR_AMD64_RMPOPT_ENABLE BIT_ULL(MSR_AMD64_RMPOPT_ENABLE_BIT) #define MSR_SVSM_CAA 0xc001f000 diff --git a/arch/x86/virt/svm/sev.c b/arch/x86/virt/svm/sev.c index e35fac0a8a3d..dc6a8e102cdc 100644 --- a/arch/x86/virt/svm/sev.c +++ b/arch/x86/virt/svm/sev.c @@ -477,6 +477,30 @@ static bool __init setup_rmptable(void) return true; } +static __init void configure_and_enable_rmpopt(void) +{ + phys_addr_t pa_start = ALIGN_DOWN(PFN_PHYS(min_low_pfn), SZ_1G); + u64 rmpopt_base = pa_start | MSR_AMD64_RMPOPT_ENABLE; + int cpu; + + if (!cpu_feature_enabled(X86_FEATURE_RMPOPT)) + return; + + if (!(rmp_cfg & MSR_AMD64_SEG_RMP_ENABLED)) { + pr_notice("RMPOPT optimizations not enabled, segmented RMP required\n"); + return; + } + + /* + * Per-CPU RMPOPT tables support at most 2 TB of addressable memory + * for RMP optimizations. Initialize the per-CPU RMPOPT table base + * to the starting physical address to enable RMP optimizations for + * up to 2 TB of system RAM on all CPUs. + */ + for_each_online_cpu(cpu) + wrmsrq_on_cpu(cpu, MSR_AMD64_RMPOPT_BASE, rmpopt_base); +} + /* * Do the necessary preparations which are verified by the firmware as * described in the SNP_INIT_EX firmware command description in the SNP @@ -530,6 +554,8 @@ int __init snp_rmptable_init(void) */ crash_kexec_post_notifiers = true; + configure_and_enable_rmpopt(); + return 0; } -- 2.43.0