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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-acaa1be9c0dsm116187766b.61.2025.04.09.08.47.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 09 Apr 2025 08:47:02 -0700 (PDT) Message-ID: <0fda3b72-8bff-4f3d-b9e2-cfe1ac1d3082@oss.qualcomm.com> Date: Wed, 9 Apr 2025 17:46:59 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/4] drm/msm/a6xx: Get HBB dynamically, if available To: Connor Abbott , Konrad Dybcio Cc: Konrad Dybcio , Bjorn Andersson , Kees Cook , "Gustavo A. R. Silva" , Rob Clark , Sean Paul , Abhinav Kumar , Dmitry Baryshkov , David Airlie , Simona Vetter , Dmitry Baryshkov , Marijn Suijten , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org References: <20250409-topic-smem_dramc-v1-0-94d505cd5593@oss.qualcomm.com> <20250409-topic-smem_dramc-v1-3-94d505cd5593@oss.qualcomm.com> <9a12e042-487b-4937-a583-709f0c37ab12@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: Ggc5XkvCKh1bLslYizrhIsat9tiXKyjQ X-Proofpoint-ORIG-GUID: Ggc5XkvCKh1bLslYizrhIsat9tiXKyjQ X-Authority-Analysis: v=2.4 cv=dbeA3WXe c=1 sm=1 tr=0 ts=67f69679 cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=EUspDBNiAAAA:8 a=VwQbUJbxAAAA:8 a=o9cw19nxWuB9g-ePJCEA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-09_05,2025-04-08_04,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 mlxlogscore=999 phishscore=0 mlxscore=0 spamscore=0 malwarescore=0 clxscore=1015 adultscore=0 priorityscore=1501 lowpriorityscore=0 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504090100 On 4/9/25 5:44 PM, Connor Abbott wrote: > On Wed, Apr 9, 2025 at 11:40 AM Konrad Dybcio > wrote: >> >> On 4/9/25 5:30 PM, Connor Abbott wrote: >>> On Wed, Apr 9, 2025 at 11:22 AM Konrad Dybcio >>> wrote: >>>> >>>> On 4/9/25 5:12 PM, Connor Abbott wrote: >>>>> On Wed, Apr 9, 2025 at 10:48 AM Konrad Dybcio wrote: >>>>>> >>>>>> From: Konrad Dybcio >>>>>> >>>>>> The Highest Bank address Bit value can change based on memory type used. >>>>>> >>>>>> Attempt to retrieve it dynamically, and fall back to a reasonable >>>>>> default (the one used prior to this change) on error. >>>>>> >>>>>> Signed-off-by: Konrad Dybcio >>>>>> --- >>>>>> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 22 ++++++++++++++++------ >>>>>> 1 file changed, 16 insertions(+), 6 deletions(-) >>>>>> >>>>>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >>>>>> index 06465bc2d0b4b128cddfcfcaf1fe4252632b6777..0cc397378c99db35315209d0265ad9223e8b55c7 100644 >>>>>> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >>>>>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >>>>>> @@ -13,6 +13,7 @@ >>>>>> #include >>>>>> #include >>>>>> #include >>>>>> +#include >>>>>> >>>>>> #define GPU_PAS_ID 13 >>>>>> >>>>>> @@ -669,17 +670,22 @@ static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu) >>>>>> static void a6xx_set_ubwc_config(struct msm_gpu *gpu) >>>>>> { >>>>>> struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); >>>>>> + u32 hbb = qcom_smem_dram_get_hbb(); >>>>>> + u32 ubwc_mode = adreno_gpu->ubwc_config.ubwc_swizzle & 1; >>>>>> + u32 level2_swizzling_dis = !(adreno_gpu->ubwc_config.ubwc_swizzle & 2); >>>>>> + u32 hbb_hi, hbb_lo; >>>>>> + >>>>>> /* >>>>>> * We subtract 13 from the highest bank bit (13 is the minimum value >>>>>> * allowed by hw) and write the lowest two bits of the remaining value >>>>>> * as hbb_lo and the one above it as hbb_hi to the hardware. >>>>>> */ >>>>>> - BUG_ON(adreno_gpu->ubwc_config.highest_bank_bit < 13); >>>>>> - u32 hbb = adreno_gpu->ubwc_config.highest_bank_bit - 13; >>>>>> - u32 hbb_hi = hbb >> 2; >>>>>> - u32 hbb_lo = hbb & 3; >>>>>> - u32 ubwc_mode = adreno_gpu->ubwc_config.ubwc_swizzle & 1; >>>>>> - u32 level2_swizzling_dis = !(adreno_gpu->ubwc_config.ubwc_swizzle & 2); >>>>>> + if (hbb < 0) >>>>>> + hbb = adreno_gpu->ubwc_config.highest_bank_bit; >>>>> >>>>> No. The value we expose to userspace must match what we program. >>>>> You'll break VK_EXT_host_image_copy otherwise. >>>> >>>> I didn't know that was exposed to userspace. >>>> >>>> The value must be altered either way - ultimately, the hardware must >>>> receive the correct information. ubwc_config doesn't seem to be const, >>>> so I can edit it there if you like it better. >>>> >>>> Konrad >>> >>> Yes, you should be calling qcom_smem_dram_get_hbb() in >>> a6xx_calc_ubwc_config(). You can already see there's a TODO there to >>> plug it in. >> >> Does this look good instead? >> >> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> index 0cc397378c99..ae8dbc250e6a 100644 >> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> @@ -588,6 +588,8 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu) >> >> static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu) >> { >> + u8 hbb; > > You can't make it u8 and then test for a negative value on error. Fair. I think it was u8 in a pre-release version of the patchset and it stuck in my mind.. though I'dve expected clang to warn me here.. > Other than that, looks good. Thanks, I'll change it in v2. Konrad