From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 75BD130674B for ; Wed, 15 Jul 2026 06:06:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784095592; cv=none; b=jJVa2kZ9S4m16i/BKmbieRzzAydoziY0/PVt9DIHkd+vdfbhLaJgcvMz/cFr3LWml1PCpAQ3nW/Zr+hLRqAeo9wWerDSKKMe1uYwI1vIT0ueoLvO+9b29VOw01pUlKPbB1faXp53OETUYruYKXBXasNkKKciIu4GufN7Qw2TXVI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784095592; c=relaxed/simple; bh=FU/fTrfu1x2zOXnH4TjfbCrXQEQPIF0X3YJyDBMbC80=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=erSWe/cNCZYM1j1t6LTGaT4Mg/t1C2+yk/rGjzUXfTK1LGIFfl02iupmzYGDoEw96QfWj0yscu6mngovaA8hRaJon960lErSBGUPRz54nE90jG7l5/TI/mDq99lC7ibs/B05IJ183/Bs9Z042CqbgX4wXbErtc8ppeuoUn3+G0I= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=LeOVttFS; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="LeOVttFS" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 521FC339; Tue, 14 Jul 2026 23:06:25 -0700 (PDT) Received: from [10.164.18.40] (unknown [10.164.18.40]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 224E33F7D8; Tue, 14 Jul 2026 23:06:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1784095589; bh=FU/fTrfu1x2zOXnH4TjfbCrXQEQPIF0X3YJyDBMbC80=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=LeOVttFSDZP9fMDZlB5HQo9yMLmX9mSD2gfJgnokZeszD4MBB42fTVxKcD7LZaz9m MeELTkQgOYh9xLjmsPjw3c3JzwN1RQUbPLP4LpzRptryNuwVLlRv1JYI/20meo5jW6 qN78exzpy/HMhms7cV90yKi4qIHNG1QEjEoKH/EI= Message-ID: <0fe2d985-3ba4-47b1-beb2-02c8d2e4a4d5@arm.com> Date: Wed, 15 Jul 2026 11:36:24 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 3/6] arm64: cpufeature: Extend bbml2_noabort support list To: Linu Cherian , Catalin Marinas , Will Deacon , Ryan Roberts , Kevin Brodsky , Suzuki K Poulose , Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20260715053408.1950475-1-linu.cherian@arm.com> <20260715053408.1950475-4-linu.cherian@arm.com> Content-Language: en-US From: Anshuman Khandual In-Reply-To: <20260715053408.1950475-4-linu.cherian@arm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 15/07/26 11:04 AM, Linu Cherian wrote: > Add below cpus to the midr list, which supports > BBML2_NOABORT. > > Cortex A520(AE) > Cortex A715 > Cortex A720(AE) > Cortex A725 > Neoverse N3 > C1-Nano > C1-Pro > C1-Ultra > C1-Premium > > C1-Ultra and C1-Premium both suffer from erratum 3683289, > where Break-Before-Make must be followed to avoid a livelock. > For both CPUs, the erratum is fixed from r1p1. > Hence we do not enable BBML2_NOABORT for CPU revisions <= r1p0. > > The relevant SDENs are: > * C1-Ultra: https://developer.arm.com/documentation/111077/9-00/ > * C1-Premium: https://developer.arm.com/documentation/111078/9-00/ > > Signed-off-by: Linu Cherian > --- > Documentation/arch/arm64/silicon-errata.rst | 4 ++++ > arch/arm64/kernel/cpufeature.c | 10 ++++++++++ > 2 files changed, 14 insertions(+) > > diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/arch/arm64/silicon-errata.rst > index 014aa1c215a1..57c778446936 100644 > --- a/Documentation/arch/arm64/silicon-errata.rst > +++ b/Documentation/arch/arm64/silicon-errata.rst > @@ -242,10 +242,14 @@ stable kernels. > +----------------+-----------------+-----------------+-----------------------------+ > | ARM | Neoverse-V3AE | #4193784 | ARM64_ERRATUM_4118414 | > +----------------+-----------------+-----------------+-----------------------------+ > +| ARM | C1-Premium | #3683289 | N/A | > ++----------------+-----------------+-----------------+-----------------------------+ > | ARM | C1-Premium | #4193780 | ARM64_ERRATUM_4118414 | > +----------------+-----------------+-----------------+-----------------------------+ > | ARM | C1-Pro | #4193714 | ARM64_ERRATUM_4193714 | > +----------------+-----------------+-----------------+-----------------------------+ > +| ARM | C1-Ultra | #3683289 | N/A | > ++----------------+-----------------+-----------------+-----------------------------+ > | ARM | C1-Ultra | #4193780 | ARM64_ERRATUM_4118414 | > +----------------+-----------------+-----------------+-----------------------------+ > | ARM | MMU-500 | #562869, | ARM_SMMU_MMU_500_CPRE_ERRATA| > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index 9a22df0c5120..1b804b6c4fe0 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -2152,6 +2152,16 @@ bool cpu_supports_bbml2_noabort(void) > MIDR_ALL_VERSIONS(MIDR_NVIDIA_OLYMPUS), > MIDR_ALL_VERSIONS(MIDR_AMPERE1), > MIDR_ALL_VERSIONS(MIDR_AMPERE1A), > + MIDR_ALL_VERSIONS(MIDR_CORTEX_A520AE), > + MIDR_ALL_VERSIONS(MIDR_CORTEX_A715), > + MIDR_ALL_VERSIONS(MIDR_CORTEX_A720AE), > + MIDR_ALL_VERSIONS(MIDR_CORTEX_A725), > + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N3), > + MIDR_ALL_VERSIONS(MIDR_C1_NANO), > + MIDR_ALL_VERSIONS(MIDR_C1_PRO), > + /* Erratum 3683289 fixed in r1p1 */ > + MIDR_REV_RANGE(MIDR_C1_ULTRA, 1, 1, 0xf), > + MIDR_REV_RANGE(MIDR_C1_PREMIUM, 1, 1, 0xf), > {} > }; > Reviewed-by: Anshuman Khandual