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On 1/23/26 17:19, Akhila YS wrote: > Convert NXP LPC18xx OTP memory controller binding to YAML format. > > Signed-off-by: Akhila YS > --- > .../devicetree/bindings/nvmem/lpc1850-otp.txt | 20 --------- > .../devicetree/bindings/nvmem/nxp,lpc1850-otp.yaml | 51 ++++++++++++++++++++++ > 2 files changed, 51 insertions(+), 20 deletions(-) > > diff --git a/Documentation/devicetree/bindings/nvmem/lpc1850-otp.txt b/Documentation/devicetree/bindings/nvmem/lpc1850-otp.txt > deleted file mode 100644 > index 853b6a754644..000000000000 > --- a/Documentation/devicetree/bindings/nvmem/lpc1850-otp.txt > +++ /dev/null > @@ -1,20 +0,0 @@ > -* NXP LPC18xx OTP memory > - > -Internal OTP (One Time Programmable) memory for NXP LPC18xx/43xx devices. > - > -Required properties: > - - compatible: Should be "nxp,lpc1850-otp" > - - reg: Must contain an entry with the physical base address and length > - for each entry in reg-names. > - - address-cells: must be set to 1. > - - size-cells: must be set to 1. > - > -See nvmem.txt for more information. > - > -Example: > - otp: otp@40045000 { > - compatible = "nxp,lpc1850-otp"; > - reg = <0x40045000 0x1000>; > - #address-cells = <1>; > - #size-cells = <1>; > - }; > diff --git a/Documentation/devicetree/bindings/nvmem/nxp,lpc1850-otp.yaml b/Documentation/devicetree/bindings/nvmem/nxp,lpc1850-otp.yaml > new file mode 100644 > index 000000000000..d37e928e7a35 > --- /dev/null > +++ b/Documentation/devicetree/bindings/nvmem/nxp,lpc1850-otp.yaml > @@ -0,0 +1,51 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/nvmem/nxp,lpc1850-otp.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: NXP LPC18xx / LPC43xx One-Time Programmable (OTP) memory > + > +maintainers: > + - Srinivas Kandagatla You may add me as a maintainer, the change is not catched by the "lpc18xx" file name pattern from a record in the MAINTAINERS file, but essentially it's an NXP LPC18xx/LPC43xx related change. > + > +description: > + The internal OTP memory in NXP LPC18xx and LPC43xx microcontrollers > + provides a dedicated non-volatile storage area designed for permanent, > + one-time configuration and data storage.The OTP controller manages write Please remove all info after the first sentence. > + protection, programming sequencing, and error detection mechanisms to > + guarantee reliable and safe permanent programming under software control. What is the source of the information above? I don't quite understand what is "error detection mechanisms" here etc. OTP controller functions are defined in SoC ROM, and it is unrelated to the described OTP memory region. > + > +allOf: > + - $ref: nvmem.yaml# > + > +properties: > + compatible: > + const: nxp,lpc1850-otp > + > + reg: > + maxItems: 1 > + > + "#address-cells": > + const: 1 > + > + "#size-cells": > + const: 1 This comes from nvmem.yaml > + > +required: > + - compatible > + - reg > + - "#address-cells" > + - "#size-cells" Please drop #address-cells/#size-cells from the list of the required properties. So far there is no user of this device tree node, and "nvmem-layout" mechanism may be preferred in future. > + > +unevaluatedProperties: false > + > +examples: > + - | > + otp@40045000 { > + compatible = "nxp,lpc1850-otp"; > + reg = <0x40045000 0x1000>; > + #address-cells = <1>; > + #size-cells = <1>; > + }; > +... > -- Best wishes, Vladimir