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[78.11.189.27]) by smtp.gmail.com with ESMTPSA id g22-20020a056512119600b00498f3ebffb2sm736362lfr.25.2022.09.29.02.39.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 29 Sep 2022 02:39:00 -0700 (PDT) Message-ID: <0fff7922-7932-dda7-f476-32f4b0d09fa0@linaro.org> Date: Thu, 29 Sep 2022 11:38:59 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.3.0 Subject: Re: [PATCHv4 1/3] dt-bindings: mmc: synopsys-dw-mshc: document "altr,sysmgr-syscon" Content-Language: en-US To: Ulf Hansson , Dinh Nguyen Cc: jh80.chung@samsung.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org References: <20220928165420.1212284-1-dinguyen@kernel.org> From: Krzysztof Kozlowski In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 29/09/2022 11:24, Ulf Hansson wrote: > On Wed, 28 Sept 2022 at 18:54, Dinh Nguyen wrote: >> >> Document the optional "altr,sysmgr-syscon" binding that is used to >> access the System Manager register that controls the SDMMC clock >> phase. >> >> Signed-off-by: Dinh Nguyen >> --- >> v4: add else statement >> v3: document that the "altr,sysmgr-syscon" binding is only applicable to >> "altr,socfpga-dw-mshc" >> v2: document "altr,sysmgr-syscon" in the MMC section >> --- >> .../bindings/mmc/synopsys-dw-mshc.yaml | 31 +++++++++++++++++-- >> 1 file changed, 28 insertions(+), 3 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml >> index ae6d6fca79e2..b73324273464 100644 >> --- a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml >> +++ b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml >> @@ -6,9 +6,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# >> >> title: Synopsys Designware Mobile Storage Host Controller Binding >> >> -allOf: >> - - $ref: "synopsys-dw-mshc-common.yaml#" >> - >> maintainers: >> - Ulf Hansson >> >> @@ -38,6 +35,34 @@ properties: >> - const: biu >> - const: ciu >> >> + altr,sysmgr-syscon: >> + $ref: /schemas/types.yaml#/definitions/phandle-array >> + items: >> + - items: >> + - description: phandle to the sysmgr node >> + - description: register offset that controls the SDMMC clock phase >> + description: >> + Contains the phandle to System Manager block that contains >> + the SDMMC clock-phase control register. The first value is the pointer >> + to the sysmgr and the 2nd value is the register offset for the SDMMC >> + clock phase register. >> + >> +allOf: >> + - $ref: "synopsys-dw-mshc-common.yaml#" >> + >> + - if: >> + properties: >> + compatible: >> + contains: >> + const: >> + - altr,socfpga-dw-mshc >> + then: >> + required: >> + - altr,sysmgr-syscon >> + else: >> + properties: >> + altr,sysmgr-syscon: false > > So this change will not be backwards compatible with existing DTBs. I > noticed that patch2 updates the DTS files for the arm64 platforms, but > there seems to be some arm32 platforms too. Isn't this going to be a > problem? > The backwards compatibility is actually expressed by the driver. If the driver keeps ABI, we can change bindings so that all DTS are being updated to pass the checks. On the other hand, the commit should express why it changes the bindings in incompatible way - this is lacking here. Best regards, Krzysztof