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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b65e8395b6csm785558866b.26.2025.10.20.04.54.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 20 Oct 2025 04:54:55 -0700 (PDT) Message-ID: <100b1a6f-0b4c-47bf-98f5-f81d05b40df2@oss.qualcomm.com> Date: Mon, 20 Oct 2025 13:54:53 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 04/24] arm64: dts: qcom: glymur: Add QUPv3 configuration for serial engines To: Jyothi Kumar Seerapu , Pankaj Patil , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250925-v3_glymur_introduction-v1-0-24b601bbecc0@oss.qualcomm.com> <20250925-v3_glymur_introduction-v1-4-24b601bbecc0@oss.qualcomm.com> <8828946b-3979-4e7b-a11c-740d8a6253ce@oss.qualcomm.com> <235cf6b7-e758-4d16-b5a1-182cc869b2e4@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <235cf6b7-e758-4d16-b5a1-182cc869b2e4@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: XBeEkCM_lXtWbEQwvizB1Nq6evziO4Jc X-Proofpoint-GUID: XBeEkCM_lXtWbEQwvizB1Nq6evziO4Jc X-Authority-Analysis: v=2.4 cv=f+5FxeyM c=1 sm=1 tr=0 ts=68f62311 cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=ZwCl7Sk8p17T5DaKarAA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=NFOGd7dJGGMPyQGDc5-O:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDE4MDAyMyBTYWx0ZWRfX42ELLWkJW7r/ Q+I5tbZE4mXXkEg0LkIYEQCt8MlebZWhpJoPdSpjvghd8ntqmSaaNlRnEMKfL/nScbxHkqoJw7R yVh1BqIVm6/lWthAR0+FUwh4UWsOuoo15VYgnnKupefJDiTLyH8VxmRiRR9p40nzpgWSoiUiEAE Kg7horj3k4zSIvIEDZ2FzH0RSfuruJfXd9V13QJxQAxAe7F8ooyVvedzLVmtyY2B8B/ev/+6XUO FHkR+0mV5fvMcqwnGS5e9Rq+nHNg69Zo0R4yEX4P2TVHqgixkHhAWiP1IOPiuxUkI1gZ5GpK88f eLfIkfDatrSb+vUXILROHXAnoOvHeKD5M+EmiEUr7FfLSLXMCcx9PlElrZYahSk7C5wjCJCI0oD 0fuFFl6Js6Q5VNMa3j/1eWofrBPT2g== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-20_02,2025-10-13_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 priorityscore=1501 impostorscore=0 suspectscore=0 adultscore=0 phishscore=0 bulkscore=0 clxscore=1015 spamscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510020000 definitions=main-2510180023 On 10/15/25 12:28 PM, Jyothi Kumar Seerapu wrote: > > > On 9/25/2025 3:48 PM, Konrad Dybcio wrote: >> On 9/25/25 8:32 AM, Pankaj Patil wrote: >>> From: Jyothi Kumar Seerapu >>> >>> Add device tree support for QUPv3 serial engine protocols on Glymur. >>> Glymur has 24 QUP serial engines across 3 QUP wrappers, each with >>> support of GPI DMA engines. >>> >>> Signed-off-by: Jyothi Kumar Seerapu >>> Signed-off-by: Pankaj Patil >>> --- >> >> [...] >> >>> +        gpi_dma2: dma-controller@800000 { >>> +            compatible = "qcom,glymur-gpi-dma", "qcom,sm6350-gpi-dma"; >>> +            reg = <0 0x00800000 0 0x60000>; >>> +            interrupts = , >>> +                     , >>> +                     , >>> +                     , >>> +                     , >>> +                     , >>> +                     , >>> +                     , >>> +                     , >>> +                     , >>> +                     , >>> +                     , >>> +                     , >>> +                     , >>> +                     , >>> +                     ; >>> +            dma-channels = <16>; >>> +            dma-channel-mask = <0x3f>; >>> +            #dma-cells = <3>; >>> +            iommus = <&apps_smmu 0xd76 0x0>; >>> +            status = "ok"; >> >> this is implied by default, drop > > Hi Konard, > > Do you mean we should remove the status property for all QUPs and GPI_DMAs from the common device tree (SOC) and enable them only in the board-specific device tree files? Nodes that are not disabled are enabled (i.e. status = "okay" as part of the initial definition is superfluous) Konrad