From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 047571A9F8C for ; Fri, 3 Jul 2026 04:42:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783053763; cv=none; b=stoH3LT+md9WMfdm0+BjgVxn9IJjMhh5eK3NxVmDdnE9nQ2l01b/1iAwyde9FARRPC2bYxVQuIn7KOK4sA8M0YHB2OUN49IQkzXMKjxoA1gp6CkhXcqCD4qoofFkhZQmnnj2+MjeoRwMHOayYgNKxI5bkD6fEByRHF9WQolLBSI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783053763; c=relaxed/simple; bh=bpC4wmpVc1FwcEVKb6RSPdMEZIiFxBvqCXgKU0+5NQI=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=IDfRpVWYZ8sthJzGfN8VFDTYV10ouhdR4QWPSwIebGooNA14NHTRmOsphaBdN/XY3d2Sny2H8EPnnzDggPbshlCl0+oZ8/4lkXETdJREByqQ8GXvMIvSx9KdXLxirMDnGbDz+1U1BsqFguF7IRgVM1TSiV2xN7BPQiAV2sKOjjw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=VNhTqcmT; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="VNhTqcmT" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E719822D7; Thu, 2 Jul 2026 21:42:28 -0700 (PDT) Received: from [10.163.170.216] (unknown [10.163.170.216]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D41F93F905; Thu, 2 Jul 2026 21:42:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1783053753; bh=bpC4wmpVc1FwcEVKb6RSPdMEZIiFxBvqCXgKU0+5NQI=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=VNhTqcmTkxr+gN1QFVp5aEJvLy7IMDZNrJ/foFduClQ6LfmhWYvSjx4EUOT9rqoSy 8ebXSbeVcj92yZVxKwg2njw/r/wxAN9UfhzV7kXRhjjS6c2tyAkJ/fOZfYLLVZBQmF ZBIr+fjrFow99uqCB+pFR6IionZ6DN1R0qIDR4yI= Message-ID: <10192896-e632-4ce9-8fd5-cdd535435581@arm.com> Date: Fri, 3 Jul 2026 10:12:28 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 0/5] Add BBML3 cpu feature To: Linu Cherian , Suzuki K Poulose Cc: Catalin Marinas , Will Deacon , Ryan Roberts , Kevin Brodsky , Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20260701094131.677636-1-linu.cherian@arm.com> <830a4d39-c829-4e79-a0ec-5a3633b58aa6@arm.com> Content-Language: en-US From: Anshuman Khandual In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 03/07/26 9:45 AM, Linu Cherian wrote: > Hi Suzuki, > > On Fri, Jul 03, 2026 at 08:47:01AM +0530, Linu Cherian wrote: >> Hi Suzuki, >> >> On Wed, Jul 01, 2026 at 11:11:35AM +0100, Suzuki K Poulose wrote: >>> On 01/07/2026 10:41, Linu Cherian wrote: >>>> Patches 1 and 2 introduces BBML3 cpu feature >>>> Patches 3, 4 and 5 adds more cpus to the BBML3 support list, >>>> which dont advertise themselves through the standard >>>> MMFR2_ID registers. >>>> >>>> Linu Cherian (5): >>>> arm64: cpufeature: Add BBML3 >>>> arm64: cpufeature: Detect BBML3 based on MMFR2 ID >>> >>> >>>> arm64: cputype: Add Cortex-A520AE definitions >>>> arm64: cputype: Add C1-Nano definitions >>>> arm64: cpufeature: Extend bbml3 support list >>> >>> If you could move the last 3 patches to the top, would be easier >>> for people to back port the "enable" BBLM3 for those CPUs, without >>> the renaming conflicts. >>> >> >> IMHO, if we change the order, "arm64: cpufeature: Extend bbml3 support list" >> title need to be tweaked and might not go well with this BBML3 support series. >> Also, backporting issue wouldnt be a problem if the whole series is >> backported and not just 3 patches in isolation ? >> > > After looking further on this, i definitely agree that moving those patches up has an > advantage, w.r.t avoiding dependency on other patches. A possible patch order could be arm64/tools/sysreg: Update ID_AA64MMFR2_EL1 arm64/cputype: Add Cortex-A520AE definitions arm64/cputype: Add C1-Nano definitions arm64/cpufeature: Extend supports_bbml2_noabort_list arm64/cpufeature: Add BBML3 arm64/cpufeature: Detect BBML3 based on MMFR2 ID