Re: i8259 and IO-APIC

[Terje Eggestad <terje.eggestad@scali.com>]

On Mon, 2002-05-27 at 16:27, Alan Cox wrote:
> On Mon, 2002-05-27 at 13:35, Terje Eggestad wrote:
> > I'm a bit curious my self, in theory the IO_APIC should drastically
> > reduce interrupt latency. An x86 has two interrupt pins, IRQ and NMI.
> 
> The APIC reduces processing overhead. The APIC bus on the pentium III is
> pretty slow (I believe its a serial 4 wire bus or similar). On the
> Athlon and Pentium IV it seems to be a lot faster.
> 
> In the case of a livelock the problem is probably the cost of handling
> the IRQ and poking slowly at the chip. Latency is pretty immaterial here
> compared with irq servicing overheads.

Do you got any numbers that state that it's processing overhead, and not
HW latency that is the bulk of interrupt service time? Just curious,
I've been looking and can't find this "perceived fact" backed up by
facts anywhere. 

BTW: according to "IA-32 Intel Arch. Software Developer's Man Vol 3"
both P3 and P4 the APIC bus is three wire, two data and one clock. 

> 
> Alan


TJ

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Terje Eggestad                  mailto:terje.eggestad@scali.no
Scali Scalable Linux Systems    http://www.scali.com

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