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Wed, 21 May 2025 07:36:26 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ThreadId: Te525b7ee476102fc Date: Wed, 21 May 2025 13:36:06 +0200 From: "Arnd Bergmann" To: "Herbert Xu" Cc: "Corentin Labbe" , "Klaus Kudielka" , "Eric Biggers" , regressions@lists.linux.dev, linux-kernel@vger.kernel.org, "Linux Crypto Mailing List" , "'bbrezillon@kernel.org'" , "EBALARD Arnaud" , "Romain Perier" Message-Id: <1024b1b7-9d58-4db4-a71a-108f6df7b623@app.fastmail.com> In-Reply-To: References: <20250515182131.GC1411@quark> <23fe1dec-032a-41fb-8e60-3a1b6c098c4e@app.fastmail.com> Subject: Re: [PATCH] crypto: marvell/cesa - Avoid empty transfer descriptor Content-Type: text/plain Content-Transfer-Encoding: 7bit On Wed, May 21, 2025, at 12:24, Herbert Xu wrote: > On Wed, May 21, 2025 at 11:58:49AM +0200, Arnd Bergmann wrote: >> >> I did not see the entire background of the discussion, but would >> point out that this is not supposed to work at all: > > We're trying to find out why this driver fails under concurrent > load. It works perfectly if you do one request at a time, but > when you hit it with load coming from both CPUs, it ends up > corrupting the data. Ok. Which SoC exactly is this on? Armada XP or Armada 385? > My suscipicion right now is DMA corruption. One common thread > seems to be that if you only use dma_map_sg it works, but if > dma_alloc_coherent memory is used then it is corrupted (this > isn't proven yet, it's just what the printk patch was showing). I see. Just a few more ideas what it could be in case it's not what you suspect: - the SRAM gets mapped into kernel space using ioremap(), which on Armada 375/38x uses MT_UNCACHED rather than MT_DEVICE as a workaround for a possible deadlock on actual MMIO registers. It's possible that the SRAM should be mapped using a different map flag to ensure it's actually consistent. If a store is posted to the SRAM, it may still be in flight at the time that the DMA master looks at it. - I see a lot of chaining of DMA descriptors, but no dma_wmb() or spinlock. A dma_wmb() or stronger (wmb, dma_mb, mb) is probably required between writing to a coherent descriptor and making it visible from another one. A spinlock is of course needed if you have multiple CPUs adding data into a shared linked list (I think this one is not shared but haven't confirmed that). Arnd