Re: PCI MMIO flushing, write-combining etc

[Alan Cox <alan@lxorguk.ukuu.org.uk>]

On Fri, 2002-08-16 at 00:45, Krzysztof Halasa wrote:
> I understand writes to PR1 can be reordered, merged, and delayed.
> What should I do to flush the write buffers? I understand reading from
> PR1 would do. Would reading from NPR2 flush PR1 write buffers?
> Would writing to NPR2 flush them?

That one I can't actually remember. 

> Now NPR2, the non-prefetchable MMIO region.
> Is it possible that the writes there are reordered, merged and/or
> delayed (delayed = not making it to the PCI device when the writel()
> completes)?

All PCI writes are posted. Think of PCI as messages otherwise you'll go
slowly insane debugging code. If you want to know your write completed
you need to read, when the read returns both have completed

> We have ioremap() and ioremap_nocache(). What is the exact difference
> between them? Would the ioremap_nocache() disable all A) read- and
> B) write-caching on a) prefetchable MMIO b) non-prefetchable MMIO ?

They make no difference