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Mon, 26 Oct 2026 22:30:59 +0000 Message-ID: <106caf0a-8644-4801-9591-80be38b39418@intel.com> Date: Mon, 26 Oct 2026 15:30:57 -0700 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH 0/8] arm,x86,fs/resctrl: Support asymmetric L2 cache allocation To: Tony Luck , Fenghua Yu , "Maciej Wieczor-Retman" , Peter Newman , James Morse , Babu Moger , Drew Fustini , Dave Martin , Chen Yu CC: , , References: <20261026215718.16810-1-tony.luck@intel.com> Content-Language: en-US From: Reinette Chatre In-Reply-To: <20261026215718.16810-1-tony.luck@intel.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: MW4PR04CA0240.namprd04.prod.outlook.com (2603:10b6:303:87::35) To SJ2PR11MB8370.namprd11.prod.outlook.com (2603:10b6:a03:540::20) X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ2PR11MB8370:EE_|PH7PR11MB5943:EE_ X-MS-Office365-Filtering-Correlation-Id: 773afc86-6617-4b0e-12c7-08df33b0cf27 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|366016|1800799024|376014|261009223027099003|261021121427099003|261022075727099003|261022105027099003|10067099003|56012099006|261026140227099003|3023799007|6133799003|18002099003|22082099003|261026121527099003|11063799006; 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N.B. it is assumned > that the only point of asymmetry is the cache bit mask length. Other > parameters must be the same (but code doesn't check). > > Overall approach is to add the per-L2 cache bitmask length to the domain > and use that everywhere instead of using a single value from the control. > > Patch 1 changes the format of the per-control "max" file and should be > merged back into Reinette's multi-control series so this file can have > a consistent format from first upstream introduction. > > Patches 2-5 are enumeration and preperation. > > Patch 6 introduces, initializes, and uses the per-domain cache bit mask > length field (arm/MPAM change needs careful scrutiny). > > Patch 7 enables asymmetric L2 for x86 CPUs that enumerate it. N.B. it > renammes the resource from "L2" to "L2A" to avoid user interface issues > with tools that expect L2 cache allocation to be symmetric. I did a quick scan and it seems to ignore the the distinction between a resource and control as highlighted the previous time you brought up this work. Specifically, please see: https://lore.kernel.org/lkml/eaeb4259-46d6-4656-8354-669ad32654b5@intel.com/ Also, why does patch #1 drop the 0x prefix from new control interface when displaying hex values to user space? This is a significant change for which patch #1 does not provide a motivation. Reinette