From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752616AbcDZHw4 (ORCPT ); Tue, 26 Apr 2016 03:52:56 -0400 Received: from mout.kundenserver.de ([217.72.192.75]:55435 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752451AbcDZHwy (ORCPT ); Tue, 26 Apr 2016 03:52:54 -0400 From: Arnd Bergmann To: linux-arm-kernel@lists.infradead.org Cc: Masahiro Yamada , Russell King , Linux Kernel Mailing List Subject: Re: [PATCH] ARM: cache-uniphier: activate ways for secondary CPUs Date: Tue, 26 Apr 2016 09:52:20 +0200 Message-ID: <10871675.TbbhfWgNkx@wuerfel> User-Agent: KMail/4.11.5 (Linux/3.16.0-10-generic; KDE/4.11.5; x86_64; ; ) In-Reply-To: References: <1460703947-12539-1-git-send-email-yamada.masahiro@socionext.com> <51817650.ZWFPAKxQiK@wuerfel> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" X-Provags-ID: V03:K0:b/HvSnbDZckvX+J0jTR+hHWlGX/e8+lLRQKBP7k+QV531O6+LNn zxnbfGtPpWR2k/87coKtupaNA7x19+Vrc942TMg+4du2vl33fIWz8o+wbfiktY7bDlZPtyH bjqm3IOs1sXDDgk4RvxoSZ+nFIo0elQQefsreS2ocSn74u/IhsD8J17pjrV1HeylWNLJmaf xQ3yPq1jifJcHhR8iWVEg== X-UI-Out-Filterresults: notjunk:1;V01:K0:r/rLVvd9orw=:ulVoidNcrLKmxuSIGufi2f +s8qkosk1PdhN3XchJjdz/zF5f/6mWpu2MLmTt+gpSLDVwh1U9MTUey2tByDAqaPpA9YomlQA R+DRzAW6TV6AZlSCRX8Al6yEoR5ckmfZj3VI18LTnaicA3ZqS1k//CMixA96mbuoBA8pKcbik n1zgmrQBi7T+ZpMzF51NOrn4RWWyDEeqSxD9A/zi3T5VxhUpgQRZADQQz3OtCMdmgUUcnIu/0 6mfswCDjVf/MnLn3GoNpxASr2Pl9sfl8phXrMHMhRRygJ+ZLxrDlQtBP2ZpOZFWiAQKCamvxF L2Uv0d4H8OmL0Mlz7hQtqIs518/QM20MXDx1RUynN2SDoqp0aP3IDRT0FdJf70hhoAxLVCrEJ CDXR1leQyHmm/0MBGMwlKCweGUP+u7DN3LacTnlKQEHe09yTf/1kon0lzBhbgo4PRvI2ZO1WW lSNnULD9R+3V0OUGqF243C2dosr72kHtuq4Ofba95I8fbRoVuHeY2m4pdNe1EgA6bg50H8Zsm XIupDuLdRx171Rlsu8HguhnAfr8piaLbVKBveomIQhVbepEqnZoiZ8hHsR+8p/hhEHLs19kqz mMC/Xcpi8xbJBxjHGLii4TaSb2iy4T0uXn8vk+GFbUGWYHKSl/AvQUlUwYzGGA73wMkXNzAnL q6jZreESV/AvxKxhbE7iBh6071faFRk50b9u21lPT7cwRkstI+LO32HE0ZHgh0WlZ5wX6l6j4 1z1g9UJ//8YgbnZy Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tuesday 26 April 2016 09:55:35 Masahiro Yamada wrote: > Hi Arnd, > > 2016-04-26 7:13 GMT+09:00 Arnd Bergmann : > > On Friday 15 April 2016 16:05:46 Masahiro Yamada wrote: > >> This outer cache allows to control active ways independently for > >> each CPU, but currently nothing is done for secondary CPUs. In > >> other words, all the ways are locked for secondary CPUs by default. > >> This commit fixes it to fully bring out the performance of this > >> outer cache. > >> > >> There would be two possible ways to achieve this: > >> > >> [1] Each CPU initializes active ways for itself. This can be done > >> via the SSCLPDAWCR register. This is a banked register, so each > >> CPU sees a different instance of the register. > >> > >> [2] The master CPU initializes active ways for all the CPUs. This > >> is available via SSCDAWCARMR(N) registers. They are mapped at > >> the address SSCDAWCARMR + 4 * N, where N is the CPU number. > >> > >> Currently, the outer cache frame work does not support a per-CPU > >> init callback. So this commit adopts [2]; the master CPU iterates > >> over possible CPUs setting up SSCDAWCARMR(N) registers. > >> > >> Unfortunately, the register offsets of SSCDAWCARMR(N) are different > >> by SoC. We can live with it by checking the version register. > >> > >> Signed-off-by: Masahiro Yamada > >> > > > > Applied to next/soc, thanks! > > > > I'm a little lost with the patches you send, could you check that > > I have applied all the ones you sent for 4.7 so far? > > > > Arnd > > > Was this one really applied, or not yet? > > My intention was to send this one just for review, > because outer-cache things are generally in Russell's field. > > If you have already applied it, I should drop it > from Russell's patch tracker. > (Sorry, I should have mentioned it.) > > Please let me know the status. Sorry, my mistake, I accidentally sent out my mail early and then did not put it into arm-soc in the end. It's not in arm-soc and it should go through Russell's patch tracker. Arnd