From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932327AbdJWOkY (ORCPT ); Mon, 23 Oct 2017 10:40:24 -0400 Received: from mx1.redhat.com ([209.132.183.28]:36604 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932225AbdJWOkX (ORCPT ); Mon, 23 Oct 2017 10:40:23 -0400 DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 42FCD7E42F Authentication-Results: ext-mx03.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx03.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=pbonzini@redhat.com Subject: Re: [PATCH 0/9] Intel Processor Trace virtulization enabling To: "Kang, Luwei" , "kvm@vger.kernel.org" Cc: "rkrcmar@redhat.com" , "tglx@linutronix.de" , "mingo@redhat.com" , "hpa@zytor.com" , "x86@kernel.org" , "linux-kernel@vger.kernel.org" , Chao Peng References: <1508155781-4576-1-git-send-email-luwei.kang@intel.com> <66f40c86-cdf3-84a7-6d42-c0c7f6850e19@redhat.com> <82D7661F83C1A047AF7DC287873BF1E167E1B5FB@SHSMSX101.ccr.corp.intel.com> <0ca0d53b-640a-c124-08dc-dbf009e01a8e@redhat.com> <82D7661F83C1A047AF7DC287873BF1E167E1B74A@SHSMSX101.ccr.corp.intel.com> <5b434733-c974-9012-0e08-48ed9e1d2fa6@redhat.com> <82D7661F83C1A047AF7DC287873BF1E167E1C475@SHSMSX101.ccr.corp.intel.com> <82D7661F83C1A047AF7DC287873BF1E167E1D731@SHSMSX101.ccr.corp.intel.com> <4ac3b093-a912-c624-f988-af03cbc33f9c@redhat.com> <82D7661F83C1A047AF7DC287873BF1E167E20AE9@SHSMSX101.ccr.corp.intel.com> From: Paolo Bonzini Message-ID: <109396fa-8f7c-8f24-e804-2a5b71ef0c64@redhat.com> Date: Mon, 23 Oct 2017 16:40:13 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.4.0 MIME-Version: 1.0 In-Reply-To: <82D7661F83C1A047AF7DC287873BF1E167E20AE9@SHSMSX101.ccr.corp.intel.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.27]); Mon, 23 Oct 2017 14:40:23 +0000 (UTC) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 23/10/2017 10:01, Kang, Luwei wrote: > >>> So, can we enable it in L1 >>> guest only first? I think it is not worth to disable EPT for L1 to >>> enable intel PT. what is your opinion? >> Yes, we can enable it. But since KVM sets IA32_VMX_MISC[14]=0, your patches must forbid enabling processor trace during VMX >> operation. > > L1 hypervisor can't get the capability of " TraceEn can be set in > VMX operation (IA32_VMX_MISC[bit 14] is 0)" and set it to 0. We need > to trap whether L1 hypervisor have enable VMXON, and forbid enable PT > when vmxon. Is that right? Or have something else? Correct. I don't have the SDM at hand, so I'm not sure what happens if you do a VMXON while TraceEn is 1. However, that has to be handled as well. Paolo