From: Christian Loehle <christian.loehle@arm.com>
To: Beata Michalska <beata.michalska@arm.com>
Cc: linux-arm-kernel@lists.infradead.org, Vladimir.Murzin@arm.com,
catalin.marinas@arm.com, will@kernel.org, suzuki.poulose@arm.com,
xuewen.yan94@gmail.com, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 3/3] arm64: topology: Reduce the skew for AMU feedback counter sampling
Date: Thu, 12 Nov 2026 09:22:46 +0000 [thread overview]
Message-ID: <10a9170d-9ec7-46be-ad0f-d364c65563cd@arm.com> (raw)
In-Reply-To: <avS3CJI82z3xDQQT@arm.com>
On 11/11/26 18:42, Beata Michalska wrote:
> On Wed, Nov 11, 2026 at 02:08:11PM +0000, Christian Loehle wrote:
>> On 11/11/26 12:39, Beata Michalska wrote:
>>> With the FFH support for CPPC, the AMU feedback counters, core and const
>>> counter, are being sampled to measure CPU performance. Checking for errata
>>> (which can affect both counters) between the reads delays the second
>>> sample and can skew the result.
>>>
>>> Take both samples in succession, then discard values from affected
>>> counters. This narrows the sampling interval used for CPPC feedback.
>>>
>>> Signed-off-by: Beata Michalska <beata.michalska@arm.com>
>>> ---
>>> arch/arm64/kernel/topology.c | 76 +++++++++++++++++++++++-------------
>>> 1 file changed, 49 insertions(+), 27 deletions(-)
>>>
>>> diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c
>>> index 66ac67bd025e..c968fa5b0c88 100644
>>> --- a/arch/arm64/kernel/topology.c
>>> +++ b/arch/arm64/kernel/topology.c
>>> @@ -381,29 +381,45 @@ enum cpc_ffh_ctr_id {
>>> CPC_FFH_CTR_CONST = 0x1,
>>> };
>>>
>>> -static void cpu_read_corecnt(void *val)
>>> +static inline void cpu_read_corecnt(void *val)
>>> {
>>> - /*
>>> - * A value of 0 can be returned if the current CPU does not support AMUs
>>> - * or if the counter is disabled for this CPU. A return value of 0 at
>>> - * counter read is properly handled as an error case by the users of the
>>> - * counter.
>>> - */
>>> - *(u64 *)val = this_cpu_has_cap(ARM64_WORKAROUND_BROKEN_AMU_CORECNT) ?
>>> - 0UL : read_corecnt();
>>> + *(u64 *)val = read_corecnt();
>>> }
>>>
>>> -static void cpu_read_constcnt(void *val)
>>> +static void cpu_try_read_corecnt(void *val)
>>> {
>>> - /*
>>> - * Return 0 if the current CPU is affected by a HW erratum.
>>> - * A value of 0 is also returned if the current CPU does not
>>> - * support AMUs or if the counter is disabled. A return
>>> - * value of 0 at counter read is properly handled as an error
>>> - * case by the users of the counter.
>>
>> Since you're moving this comment around, AFAICT it's not actually true?
>> cpu_has_amu_feat() is checked (which will return -EOPNOTSUPP) before
>> landing here, right?
>>
> Not entirely, no.
> `cpu_has_amu_feat()` verifies the support for AMUs, the extension itself
> (ID_AA64PFR0_EL1). Workarounds are applied on top of it.
Right, I was only referring to:
"A value of 0 is also returned if the current CPU does not support AMUs[...]"
> [snip]
prev parent reply other threads:[~2026-11-12 9:22 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-11 12:39 [PATCH 0/3] arm64: errata: Update AMU workarounds Beata Michalska
2026-11-11 12:39 ` [PATCH 1/3] arm64: errata: Extend the workaround for broken AMEVCNTR01 counter Beata Michalska
2026-11-11 12:39 ` [PATCH 2/3] arm64: errata: Add Cortex-A715/A720 AMU core counter workaround Beata Michalska
2026-11-11 12:39 ` [PATCH 3/3] arm64: topology: Reduce the skew for AMU feedback counter sampling Beata Michalska
2026-11-11 13:56 ` Christian Loehle
2026-11-11 18:38 ` Beata Michalska
2026-11-12 9:10 ` Christian Loehle
2026-11-11 14:08 ` Christian Loehle
2026-11-11 18:42 ` Beata Michalska
2026-11-12 9:22 ` Christian Loehle [this message]
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