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Wed, 16 Jun 2021 07:54:49 +0000 Received: from [10.26.49.10] (172.20.187.5) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 16 Jun 2021 07:54:46 +0000 Subject: Re: Query regarding the use of pcie-designware-plat.c file To: Bjorn Helgaas CC: Vidya Sagar , , , , , , , , Thierry Reding , Krishna Thota , , References: <20210615194209.GA2908457@bjorn-Precision-5520> From: Jon Hunter Message-ID: <10a92c35-6e4d-0428-079c-7e98ff6e9414@nvidia.com> Date: Wed, 16 Jun 2021 08:54:44 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.8.1 MIME-Version: 1.0 In-Reply-To: <20210615194209.GA2908457@bjorn-Precision-5520> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [172.20.187.5] X-ClientProxiedBy: HQMAIL101.nvidia.com (172.20.187.10) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 20fb257a-973c-48a8-f480-08d9309c0442 X-MS-TrafficTypeDiagnostic: CY4PR12MB1446: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8882; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jun 2021 07:54:49.2644 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 20fb257a-973c-48a8-f480-08d9309c0442 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.34];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT035.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR12MB1446 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 15/06/2021 20:42, Bjorn Helgaas wrote: > On Wed, Jun 09, 2021 at 05:54:38PM +0100, Jon Hunter wrote: >> >> On 09/06/2021 17:30, Bjorn Helgaas wrote: >>> On Wed, Jun 09, 2021 at 12:52:37AM +0530, Vidya Sagar wrote: >>>> Hi, >>>> I would like to know what is the use of pcie-designware-plat.c file. This >>>> looks like a skeleton file and can't really work with any specific hardware >>>> as such. >>>> Some context for this mail thread is, if the config CONFIG_PCIE_DW_PLAT is >>>> enabled in a system where a Synopsys DesignWare IP based PCIe controller is >>>> present and its configuration is enabled (Ex:- Tegra194 system with >>>> CONFIG_PCIE_TEGRA194_HOST enabled), then, it can so happen that the probe of >>>> pcie-designware-plat.c called first (because all DWC based PCIe controller >>>> nodes have "snps,dw-pcie" compatibility string) and can crash the system. >>> >>> What's the crash? If a device claims to be compatible with >>> "snps,dw-pcie" and pcie-designware-plat.c claims to know how to >>> operate "snps,dw-pcie" devices, it seems like something is wrong. >>> >>> "snps,dw-pcie" is a generic device type, so pcie-designware-plat.c >>> might not know how to operate device-specific details of some of those >>> devices, but basic functionality should work and it certainly >>> shouldn't crash. >> >> It is not really a crash but a hang when trying to access the hardware >> before it has been properly initialised. > > This doesn't really answer my question. > > If the hardware claims to be compatible with "snps,dw-pcie" and a > driver knows how to operate "snps,dw-pcie" devices, it should work. > > If the hardware requires initialization that is not part of the > "snps,dw-pcie" programming model, it should not claim to be compatible > with "snps,dw-pcie". Or, if pcie-designware-plat.c is missing some > init that *is* part of the programming model, maybe it needs to be > enhanced? Right and this is exactly why I removed the compatible string "snps,dw-pcie" for Tegra194 because it is clear that this does not work and hence not compatible. Sagar is purely trying to understand if this is case of other devices as well or just Tegra194. Jon -- nvpublic