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[96.230.100.15]) by smtp.gmail.com with ESMTPSA id d6sm8080823qtb.55.2022.02.08.14.02.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Feb 2022 14:02:20 -0800 (PST) Message-ID: <10bfefe40b9cb82610d4f1e8d3e7293824fac03b.camel@redhat.com> Subject: Re: [PATCH] drm/i915/psr: Disable PSR2 selective fetch for all TGL steps From: Lyude Paul To: "Souza, Jose" , "dri-devel@lists.freedesktop.org" , "intel-gfx@lists.freedesktop.org" Cc: "airlied@linux.ie" , "ville.syrjala@linux.intel.com" , "Vivi, Rodrigo" , "joonas.lahtinen@linux.intel.com" , "Mun, Gwan-gyeong" , "Roper, Matthew D" , "tvrtko.ursulin@linux.intel.com" , "Kahola, Mika" , "linux-kernel@vger.kernel.org" , "stable@vger.kernel.org" , "jani.nikula@linux.intel.com" , "daniel@ffwll.ch" , "Hogander, Jouni" , "De Marchi, Lucas" Date: Tue, 08 Feb 2022 17:02:18 -0500 In-Reply-To: <47eed687da699a6abbfd7726439fd307786c9d93.camel@intel.com> References: <20220207213923.3605-1-lyude@redhat.com> <47eed687da699a6abbfd7726439fd307786c9d93.camel@intel.com> Organization: Red Hat Inc. Content-Type: text/plain; charset="UTF-8" User-Agent: Evolution 3.42.3 (3.42.3-1.fc35) MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Opened the issue at https://gitlab.freedesktop.org/drm/intel/-/issues/5077 , included dmesg + video. Feel free to let me know if you need any more info, or need me to try any patches On Tue, 2022-02-08 at 13:06 +0000, Souza, Jose wrote: > On Mon, 2022-02-07 at 16:38 -0500, Lyude Paul wrote: > > As we've unfortunately started to come to expect from PSR on Intel > > platforms, PSR2 selective fetch is not at all ready to be enabled on > > Tigerlake as it results in severe flickering issues - at least on this > > ThinkPad X1 Carbon 9th generation. The easiest way I've found of > > reproducing these issues is to just move the cursor around the left border > > of the screen (suspicious…). > > Where is the bug for that? Where is the logs? > We can't go from enabled to disabled without any debug and because of a > single device. > In the mean time you have the option to set the i915 parameter to disable > it. > > > > > So, fix people's displays again and turn PSR2 selective fetch off for all > > steppings of Tigerlake. This can be re-enabled again if someone from Intel > > finds the time to fix this functionality on OEM machines. > > > > Signed-off-by: Lyude Paul > > Fixes: 7f6002e58025 ("drm/i915/display: Enable PSR2 selective fetch by > > default") > > Cc: Gwan-gyeong Mun > > Cc: Ville Syrjälä > > Cc: José Roberto de Souza > > Cc: Jani Nikula > > Cc: Rodrigo Vivi > > Cc: intel-gfx@lists.freedesktop.org > > Cc: # v5.16+ > > --- > >  drivers/gpu/drm/i915/display/intel_psr.c | 10 +++++++--- > >  1 file changed, 7 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > > b/drivers/gpu/drm/i915/display/intel_psr.c > > index a1a663f362e7..25c16abcd9cd 100644 > > --- a/drivers/gpu/drm/i915/display/intel_psr.c > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > > @@ -737,10 +737,14 @@ static bool intel_psr2_sel_fetch_config_valid(struct > > intel_dp *intel_dp, > >                 return false; > >         } > >   > > -       /* Wa_14010254185 Wa_14010103792 */ > > -       if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) { > > +       /* > > +        * There's two things stopping this from being enabled on TGL: > > +        * For steps A0-C0: workarounds Wa_14010254185 Wa_14010103792 are > > missing > > +        * For all steps: PSR2 selective fetch causes screen flickering > > +        */ > > +       if (IS_TIGERLAKE(dev_priv)) { > >                 drm_dbg_kms(&dev_priv->drm, > > -                           "PSR2 sel fetch not enabled, missing the > > implementation of WAs\n"); > > +                           "PSR2 sel fetch not enabled, currently broken > > on TGL\n"); > >                 return false; > >         } > >   > -- Cheers, Lyude Paul (she/her) Software Engineer at Red Hat