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Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones , Alim Akhtar , Peter Griffin , =?UTF-8?Q?Andr=C3=A9_Draszik?= , Bartlomiej Zolnierkiewicz , Kees Cook , "Gustavo A. R. Silva" , willmcvicker@google.com, jyescas@google.com, shin.son@samsung.com, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-hardening@vger.kernel.org References: <20260114-acpm-tmu-v1-0-cfe56d93e90f@linaro.org> <20260114-acpm-tmu-v1-1-cfe56d93e90f@linaro.org> <20260115-ultramarine-wildebeest-of-completion-ea1bc0@quoll> Content-Language: en-US From: Tudor Ambarus In-Reply-To: <20260115-ultramarine-wildebeest-of-completion-ea1bc0@quoll> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 1/15/26 3:32 PM, Krzysztof Kozlowski wrote: > On Wed, Jan 14, 2026 at 02:16:29PM +0000, Tudor Ambarus wrote: >> Add device tree bindings for the Google GS101 Thermal Management Unit >> (TMU). >> >> The GS101 TMU is a hybrid thermal solution: >> 1. Configuration (thresholds, hysteresis) is handled via the Alive >> Clock and Power Manager (ACPM) firmware protocol. >> 2. Interrupt handling is handled by the kernel via direct register >> access. >> >> This binding documents the required resources, including the APB clock >> for register access and the phandle to the associated syscon node. >> >> Signed-off-by: Tudor Ambarus >> --- >> .../bindings/thermal/google,gs101-tmu-top.yaml | 64 ++++++++++++++++++++++ >> 1 file changed, 64 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/thermal/google,gs101-tmu-top.yaml b/Documentation/devicetree/bindings/thermal/google,gs101-tmu-top.yaml >> new file mode 100644 >> index 0000000000000000000000000000000000000000..ecf4a315ecf1ea0649c4e96a207d531c696282f4 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/thermal/google,gs101-tmu-top.yaml >> @@ -0,0 +1,64 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/thermal/google,gs101-tmu-top.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Google GS101 Thermal Management Unit (TMU) >> + >> +maintainers: >> + - Tudor Ambarus >> + >> +description: | >> + The Google GS101 TMU is a thermal sensor block managed via the ACPM >> + (Active Core Power Management) firmware. While the firmware handles >> + the thermal algorithm and thresholds, the kernel requires direct >> + access to the interrupt pending registers via a syscon interface to >> + acknowledge and clear thermal interrupts. >> + >> +properties: >> + compatible: >> + const: google,gs101-tmu-top >> + >> + clocks: >> + maxItems: 1 >> + description: | >> + Phandle to the APB peripheral clock (PCLK) required to access >> + the TMU registers. > > Drop all the redundancies, so: > items: > - description: APB peripheral clock (PCLK) for TMU register access > ack > >> + >> + interrupts: >> + maxItems: 1 >> + description: | >> + The combined thermal interrupt signal (Level High). > > Drop description > ack >> + >> + syscon: > > I feel like suddenly you sent something completely different than what > have you been working for the past 4 years. > >> + $ref: /schemas/types.yaml#/definitions/phandle >> + description: | >> + Phandle to the device node representing the TMU System Controller >> + (compatible with "google,gs101-tmu-syscon"). This node provides the >> + regmap for INTPEND and INTCLEAR registers. >> + >> + "#thermal-sensor-cells": >> + const: 1 >> + > > No supply? It seems not. Nothing specified downstream. Couldn't find anything in the schematics that I have either. I addressed the rest of the feedback in v2. Thanks, ta