Re: [PATCH v2 17/46] drm/mediatek: Add support for hardware multi-stage layers

["CK Hu (胡俊光)" <ck.hu@mediatek.com>]

On Tue, 2026-07-14 at 13:43 +0200, AngeloGioacchino Del Regno wrote:
> In preparation for adding support for newer, more complex, display
> controllers like the ones found in the MediaTek Kompanio Ultra and
> Genio Pro 5100 (MT8196/MT8894), add support for multi-stage layers
> as in newer hardware, there is a special strategy using multiple
> hardware components of one (or multiple) display controller(s) to
> form one single layer.
> 
> Multi-stage layers are one more step towards extra flexibility of
> the Display Subsystem, making it possible to change capabilities
> of Display Controller Pipelines depending on the final application
> of a board: for example, one board may choose to use fewer layers
> per pipeline to achieve more pipelines (more concurrent outputs),
> or more layers to achieve less, but more capable (as in offloading
> and in achievable bandwidth) concurrent outputs.
> 
> This currently adds boilerplate to support this hardware, but does
> not yet implement the IP-specific support for MT8196/8894, which
> will be done after all preparation is done.

Could you add mt8196 support based on original layer architecture first then introduce this multi-stage architecture?
This series is so large and I would like to break it into multiple series.
For other upstreamed SoC, the hardware also has some flexibility to route display pipeline,
but we still implement the fixed pipeline first.
This suggestion just want to simplify the review process.

> 
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---

[snip]

> +static void mtk_crtc_config_layer(struct mtk_crtc *mtk_crtc,
> +				  struct mtk_plane_state *plane_state,
> +				  int layer_num, struct cmdq_pkt *cmdq_pkt)
> +{
> +	u8 *layer_stages = mtk_crtc->hwlayers[layer_num].layer_stages;
> +	u8 i = 0;

In mtk_ddp_comp_for_plane(), it consider mt8183 main path which two component has OVL layers: OVL0 and OVL_2L0.
That crtc has 6 planes.
When calling mtk_ddp_comp_layer_config() with OVL_2L0, the layer_num would be 0 or 1 not 4 or 5.
So add this adjustment like mtk_ddp_comp_for_plane().

I would not review rest part because you may base on a wrong assumption to implement.

Regards,
CK

> +
> +	do {
> +		mtk_ddp_comp_layer_config(mtk_crtc->ddp_comp[layer_stages[i]],
> +					  layer_num, plane_state, cmdq_pkt);
> +	} while (++i < mtk_crtc->hwlayers[layer_num].layer_stages_nr);
> +
> +	return;
> +}
> +