mirror of https://lore.kernel.org/lkml/
 help / color / mirror / Atom feed
From: Marc Zyngier <marc.zyngier@arm.com>
To: Will Deacon <will.deacon@arm.com>, linux-arm-kernel@lists.infradead.org
Cc: mark.rutland@arm.com, kim.phillips@arm.com,
	alex.bennee@linaro.org, christoffer.dall@linaro.org,
	tglx@linutronix.de, peterz@infradead.org,
	alexander.shishkin@linux.intel.com, robh@kernel.org,
	suzuki.poulose@arm.com, pawel.moll@arm.com,
	mathieu.poirier@linaro.org, mingo@redhat.com,
	linux-kernel@vger.kernel.org
Subject: Re: [RFC PATCH v2 04/10] arm64: head.S: Enable EL1 (host) access to SPE when entered at EL2
Date: Fri, 13 Jan 2017 19:21:14 +0000	[thread overview]
Message-ID: <110f31fc-4480-6218-0e7c-1576cb5368ba@arm.com> (raw)
In-Reply-To: <1484323429-15231-5-git-send-email-will.deacon@arm.com>

On 13/01/17 16:03, Will Deacon wrote:
> The SPE architecture requires each exception level to enable access
> to the SPE controls for the exception level below it, since additional
> context-switch logic may be required to handle the buffer safely.
> 
> This patch allows EL1 (host) access to the SPE controls when entered at
> EL2.
> 
> Cc: Marc Zyngier <marc.zyngier@arm.com>
> Signed-off-by: Will Deacon <will.deacon@arm.com>
> ---
>  arch/arm64/kernel/head.S | 14 ++++++++++++--
>  1 file changed, 12 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
> index 4b1abac3485a..6a97831dcf3b 100644
> --- a/arch/arm64/kernel/head.S
> +++ b/arch/arm64/kernel/head.S
> @@ -592,8 +592,8 @@ CPU_LE(	movk	x0, #0x30d0, lsl #16	)	// Clear EE and E0E on LE systems
>  #endif
>  
>  	/* EL2 debug */
> -	mrs	x0, id_aa64dfr0_el1		// Check ID_AA64DFR0_EL1 PMUVer
> -	sbfx	x0, x0, #8, #4
> +	mrs	x1, id_aa64dfr0_el1		// Check ID_AA64DFR0_EL1 PMUVer
> +	sbfx	x0, x1, #8, #4
>  	cmp	x0, #1
>  	b.lt	4f				// Skip if no PMU present
>  	mrs	x0, pmcr_el0			// Disable debug access traps
> @@ -601,6 +601,16 @@ CPU_LE(	movk	x0, #0x30d0, lsl #16	)	// Clear EE and E0E on LE systems
>  4:
>  	csel	x0, xzr, x0, lt			// all PMU counters from EL1
>  	msr	mdcr_el2, x0			// (if they exist)
> +	/* Statistical profiling */
> +	ubfx	x0, x1, #32, #4			// Check ID_AA64DFR0_EL1 PMSVer
> +	cbz	x0, 5f				// Skip if SPE not present
> +	mrs	x0, mdcr_el2			// Preserve HPMN field
> +	cmp	x2, xzr				// If VHE is not enabled,
> +	mov	x1, #3				// use EL1&0 translations,
> +	cinc	x1, x1, ne			// otherwise use EL2 and
> +	bfi	x0, x1, #12, #3			// enable/disable access
> +	msr	mdcr_el2, x0			// traps accordingly.

Man, this hack to set TPMS and E2PB is horrid. It does the trick, but it
took me a couple of minutes to realize what it was doing. Can't we just
have named flags and a some form of conditional select instead? It would
hurt a lot less...

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...

  reply	other threads:[~2017-01-13 19:21 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-01-13 16:03 [RFC PATCH v2 00/10] Add support for the ARMv8.2 Statistical Profiling Extension Will Deacon
2017-01-13 16:03 ` [RFC PATCH v2 01/10] arm64: cpufeature: allow for version discrepancy in PMU implementations Will Deacon
2017-01-13 16:03 ` [RFC PATCH v2 02/10] arm64: cpufeature: Don't enforce system-wide SPE capability Will Deacon
2017-01-13 16:03 ` [RFC PATCH v2 03/10] arm64: KVM: Save/restore the host SPE state when entering/leaving a VM Will Deacon
2017-01-16 11:25   ` Marc Zyngier
2017-01-18 15:24     ` Will Deacon
2017-01-13 16:03 ` [RFC PATCH v2 04/10] arm64: head.S: Enable EL1 (host) access to SPE when entered at EL2 Will Deacon
2017-01-13 19:21   ` Marc Zyngier [this message]
2017-01-13 16:03 ` [RFC PATCH v2 05/10] genirq: export irq_get_percpu_devid_partition to modules Will Deacon
2017-01-13 19:04   ` Marc Zyngier
2017-01-16  9:06   ` Thomas Gleixner
2017-01-13 16:03 ` [RFC PATCH v2 06/10] perf/core: Export AUX buffer helpers " Will Deacon
2017-01-13 16:03 ` [RFC PATCH v2 07/10] perf: Directly pass PERF_AUX_* flags to perf_aux_output_end Will Deacon
2017-01-13 16:03 ` [RFC PATCH v2 08/10] perf/core: Add PERF_AUX_FLAG_COLLISION to report colliding samples Will Deacon
2017-01-13 16:03 ` [RFC PATCH v2 09/10] drivers/perf: Add support for ARMv8.2 Statistical Profiling Extension Will Deacon
2017-01-13 16:40   ` Kim Phillips
2017-01-13 17:03     ` Will Deacon
2017-01-13 18:17       ` Kim Phillips
2017-01-13 16:03 ` [RFC PATCH v2 10/10] dt-bindings: Document devicetree binding for ARM SPE Will Deacon
2017-01-13 18:43   ` Mark Rutland
2017-01-16 10:59     ` Will Deacon
2017-01-17 16:31       ` Kim Phillips
2017-01-17 16:50         ` Mark Rutland
2017-01-17 16:45       ` Mark Rutland

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=110f31fc-4480-6218-0e7c-1576cb5368ba@arm.com \
    --to=marc.zyngier@arm.com \
    --cc=alex.bennee@linaro.org \
    --cc=alexander.shishkin@linux.intel.com \
    --cc=christoffer.dall@linaro.org \
    --cc=kim.phillips@arm.com \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=mark.rutland@arm.com \
    --cc=mathieu.poirier@linaro.org \
    --cc=mingo@redhat.com \
    --cc=pawel.moll@arm.com \
    --cc=peterz@infradead.org \
    --cc=robh@kernel.org \
    --cc=suzuki.poulose@arm.com \
    --cc=tglx@linutronix.de \
    --cc=will.deacon@arm.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox

all inboxes | Powered by JetHome®