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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-bb986113ee2sm63917166b.55.2026.04.29.02.18.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 29 Apr 2026 02:18:21 -0700 (PDT) Message-ID: <1120b76e-3c98-4f32-821f-baab667dfc38@oss.qualcomm.com> Date: Wed, 29 Apr 2026 11:18:18 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH RFC v3 07/11] clk: qcom: gcc-msm8939: mark Venus core GDSCs as hardware controlled To: Bryan O'Donoghue , Erikas Bitovtas , Vikash Garodia , Dikshita Agarwal , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , =?UTF-8?Q?Andr=C3=A9_Apitzsch?= , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org References: <20260427-msm8939-venus-rfc-v3-0-288195bb7917@gmail.com> <9kBbj8Jr-f6eqC6XfnJPf3gKQD-3WfzXgzl4KEVKhRZlW2_GftgFBsijqUgEvGcgmeFqPwtVquMmibHUMaR_sQ==@protonmail.internalid> <20260427-msm8939-venus-rfc-v3-7-288195bb7917@gmail.com> <0ee6bf23-17a3-4a7c-93d2-276e97cc3a14@kernel.org> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <0ee6bf23-17a3-4a7c-93d2-276e97cc3a14@kernel.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: rYTkmxe2SIsHNRFuNY5h45OMOS4oCPQ4 X-Authority-Analysis: v=2.4 cv=A4dc+aWG c=1 sm=1 tr=0 ts=69f1ccdf cx=c_pps a=ULNsgckmlI/WJG3HAyAuOQ==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=pGLkceISAAAA:8 a=2ZlRtKr-XBrgk40BSoUA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=1WsBpfsz9X-RYQiigVTh:22 X-Proofpoint-ORIG-GUID: rYTkmxe2SIsHNRFuNY5h45OMOS4oCPQ4 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDI5MDA5MiBTYWx0ZWRfX2zBP7skoXG91 P00T3znlS28usplzoWsMiw6+u51QQT70/KK+E7OA9sIzGKCRJdRh/DFaMj+SGW/Rgzxibz+0uJ4 L/+1+ANXvYLocF2XQCg0xvYCogSw7zvn2RxlJIsKtT6isd4C9t1BSkTUpdHZH96+f/4G1PG1Op7 bQrNvxJz1A/xQp9iV8cHeEp6bOpTYCKmmXmpESoXFJNZjx91b9iA64UcY0TsfS95/Smdr8hKiZl mUeh/cFzbq902NA+OxXrPAXgoxTudIGp2AGZkc7lf6yr3dsJwxVUKYEzLbjkvi3E8iW1xxbhjbH sxH1SiGgyOV5dYq9tUpJBv/o7KYcYucsC7FWfdyH6M9Ez3bfkX0a6rdo+ypqmbrjnPsDBNLpTjK xNripguwZSnJ2tOtQ+SFMOToeRy09ZmwmtgxiI/HKbWNvVRq18XMz+4KU80FNZ7M65jvJvs1pR6 vqxPNnYSb8Bj9SzVmVw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-28_05,2026-04-28_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 suspectscore=0 malwarescore=0 lowpriorityscore=0 priorityscore=1501 phishscore=0 bulkscore=0 impostorscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604290092 On 4/29/26 6:14 AM, Bryan O'Donoghue wrote: > On 27/04/2026 18:58, Erikas Bitovtas wrote: >> Since in downstream kernel VENUS_CORE0_GDSC and VENUS_CORE1_GDSC have a >> device tree property "qcom,supports-hw-trigger", add a HW_CTRL flag >> to these GDSCs to indicate that they are hardware controlled. >> >> Venus core clock cannot be enabled if Venus core GDSCs are switched off. >> But since they are hardware controlled, they can be switched off at >> any moment. Vote for the Venus core clock to enable it later when GDSCs >> get turned on. >> >> Signed-off-by: Erikas Bitovtas >> --- >>   drivers/clk/qcom/gcc-msm8939.c | 4 ++++ >>   1 file changed, 4 insertions(+) >> >> diff --git a/drivers/clk/qcom/gcc-msm8939.c b/drivers/clk/qcom/gcc-msm8939.c >> index 45193b3d714b..420997b00ae0 100644 >> --- a/drivers/clk/qcom/gcc-msm8939.c >> +++ b/drivers/clk/qcom/gcc-msm8939.c >> @@ -3664,6 +3664,7 @@ static struct clk_branch gcc_venus0_vcodec0_clk = { >> >>   static struct clk_branch gcc_venus0_core0_vcodec0_clk = { >>       .halt_reg = 0x4c02c, >> +    .halt_check = BRANCH_HALT_SKIP, >>       .clkr = { >>           .enable_reg = 0x4c02c, >>           .enable_mask = BIT(0), >> @@ -3681,6 +3682,7 @@ static struct clk_branch gcc_venus0_core0_vcodec0_clk = { >> >>   static struct clk_branch gcc_venus0_core1_vcodec0_clk = { >>       .halt_reg = 0x4c034, >> +    .halt_check = BRANCH_HALT_SKIP, >>       .clkr = { >>           .enable_reg = 0x4c034, >>           .enable_mask = BIT(0), >> @@ -3753,6 +3755,7 @@ static struct gdsc venus_core0_gdsc = { >>       .pd = { >>           .name = "venus_core0", >>       }, >> +    .flags = HW_CTRL, >>       .pwrsts = PWRSTS_OFF_ON, >>   }; >> >> @@ -3761,6 +3764,7 @@ static struct gdsc venus_core1_gdsc = { >>       .pd = { >>           .name = "venus_core1", >>       }, >> +    .flags = HW_CTRL, >>       .pwrsts = PWRSTS_OFF_ON, >>   }; >> >> >> -- >> 2.54.0 >> > > The downstream opts to put the GDSC under hw control, which is not the same thing as it being under hw control, its up to you to put it under hw control. > > So you might want to be more conservative especially given you have a problem getting the encoder and decoder to run simultaneously - I might try parking this patch and then see what happens. i.e., Bryan is asking you to replace HW_CTRL with HW_CTRL_TRIGGER Konrad