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This update configures the SPI controller to use a 4-bit bus width for both transmission and reception, potentially improving SPI throughput and matching the hardware capabilities more closely. Signed-off-by: Fong, Yan Kei Reviewed-by: Khairul Anuar Romli Reviewed-by: Matthew Gerlach --- arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts index b31cfa6b802d..9ee312bae8d2 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts @@ -116,6 +116,8 @@ flash@0 { cdns,tsd2d-ns = <50>; cdns,tchsh-ns = <4>; cdns,tslch-ns = <4>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; partitions { compatible = "fixed-partitions"; -- 2.25.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from PH0PR06CU001.outbound.protection.outlook.com (mail-westus3azon11011039.outbound.protection.outlook.com [40.107.208.39]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4ED21221FDD; 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This update configures the SPI controller to use a 4-bit bus width for both transmission and reception, potentially improving SPI throughput and matching the hardware capabilities more closely. Signed-off-by: Fong, Yan Kei Reviewed-by: Khairul Anuar Romli Reviewed-by: Matthew Gerlach --- arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts index b31cfa6b802d..9ee312bae8d2 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts @@ -116,6 +116,8 @@ flash@0 { cdns,tsd2d-ns = <50>; cdns,tchsh-ns = <4>; cdns,tslch-ns = <4>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; partitions { compatible = "fixed-partitions"; -- 2.25.1