On Tue, 2005-09-13 at 07:25 -0700, Linus Torvalds wrote: > > On Mon, 12 Sep 2005, Norbert Kiesel wrote: > > > > diff is appended. Regarding the -rc3 and friends, currently I can't as > > I jumped directly from 12.5 to 13. This is my desktop at work, so I > > try to keep it somewhat stable. However, if you have a guess which > > versions to try, I can give it a spin. It takes some time though to > > test, as the lockup normally only happens after 1 hour or so (although > > I could propably speed this up by doing lots of disk IO). > > No need. The numbers made it clear: this is the same bug that hit the > hpt366 driver: > > 0000:00:10.0 RAID bus controller: Silicon Image, Inc. SiI 0649 > Ultra ATA/100 PCI to ATA Host Controller (rev 01) > ... > 00: 95 10 49 06 07 00 90 02 01 00 04 01 00 40 00 00 > 10: 01 b8 00 00 01 bc 00 00 01 c0 00 00 01 c4 00 00 > 20: 01 c8 00 00 00 00 00 00 00 00 00 00 95 10 49 06 > -30: 00 00 00 00 60 00 00 00 00 00 00 00 0c 01 02 04 > +30: 01 00 00 00 60 00 00 00 00 00 00 00 0c 01 02 04 > > and the exact same cause too. > > I wonder who the _hell_ has been sprinkling these _byte_ writes to the ROM > enable logic around? > > I bet this will fix it.. > > Linus > --- > diff --git a/drivers/ide/pci/cmd64x.c b/drivers/ide/pci/cmd64x.c > --- a/drivers/ide/pci/cmd64x.c > +++ b/drivers/ide/pci/cmd64x.c > @@ -608,7 +608,7 @@ static unsigned int __devinit init_chips > > #ifdef __i386__ > if (dev->resource[PCI_ROM_RESOURCE].start) { > - pci_write_config_byte(dev, PCI_ROM_ADDRESS, dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE); > + pci_write_config_dword(dev, PCI_ROM_ADDRESS, dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE); > printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n", name, dev->resource[PCI_ROM_RESOURCE].start); > } > #endif > Ok, I applied the patch and I'm running it right now, so far so good. Here is the the output of lspci from the patched 2.6.13.1 (not sure if a diff to the unpatched 2.6.13.1 or the 2.6.12.5 would be more useful, so I settled for no diff :-). 0000:00:00.0 Host bridge: VIA Technologies, Inc. VT8363/8365 [KT133/KM133] (rev 02) Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- SERR- TAbort- SERR- Reset- FastB2B- Capabilities: [80] Power Management version 2 Flags: PMEClk- DSI- D1+ D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00: 06 11 05 83 07 00 30 22 00 00 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 01 01 00 90 90 00 00 20: 00 e4 f0 e5 00 d0 f0 df 00 00 00 00 00 00 00 00 30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 0c 00 0000:00:07.0 ISA bridge: VIA Technologies, Inc. VT82C686 [Apollo Super South] (rev 22) Subsystem: VIA Technologies, Inc. VT82C686/A PCI to ISA Bridge Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping+ SERR- FastB2B- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR-