From: Arjan van de Ven <arjan@infradead.org>
To: ddaney@avtrex.com
Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org
Subject: Re: Patch: ATI Xilleon port 2/11 net/e100 Memory barriers and write flushing
Date: Thu, 20 Oct 2005 09:47:25 +0200 [thread overview]
Message-ID: <1129794446.2807.3.camel@laptopd505.fenrus.org> (raw)
In-Reply-To: <17239.12568.110253.404667@dl2.hq2.avtrex.com>
On Wed, 2005-10-19 at 22:54 -0700, David Daney wrote:
> This is the second part of my Xilleon port.
>
> I am sending the full set of patches to linux-mips@linux-mips.org
> which is archived at: http://www.linux-mips.org/archives/
>
> Only the patches that touch generic parts of the kernel are coming
> here.
>
> The Xilleon (32bit MIPS SOC) has a write back buffer that seems to
> operate on the pci bus and does not get flushed before a read. The
> result is that a memory barrier must be done before a read intended to
> flush PCI writes.
this is broken hardware; the real solution is to put that wmb() into the
readl() function, as opposed to patching half the kernel for this!
And the second problem seems to be an reodering, which is also not quite
allowed. That also needs fixing, probably in the writel/writeb() macros.
next prev parent reply other threads:[~2005-10-20 7:47 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2005-10-20 5:54 David Daney
2005-10-20 7:47 ` Arjan van de Ven [this message]
2005-10-20 19:01 ` Jesse Brandeburg
2005-10-21 8:36 ` Ralf Baechle
2005-10-21 16:01 ` David Daney
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