From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
To: Alan Stern <stern@rowland.harvard.edu>
Cc: Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
Greg Kroah-Hartman <gregkh@suse.de>,
Linus Torvalds <torvalds@g5.osdl.org>
Subject: Re: [PATCH] UHCI: add missing memory barriers
Date: Sat, 17 Dec 2005 16:55:47 +1100 [thread overview]
Message-ID: <1134798947.6102.31.camel@gaston> (raw)
In-Reply-To: <Pine.LNX.4.44L0.0512162216580.15902-100000@netrider.rowland.org>
> Looking at the PCI code, I see that the accesses are protected by a
> spinlock. Does that guarantee in-order execution of writes to
> configuration space with respect to writes to regular memory? On all
> platforms? If yes, then this barrier is not needed.
Hrm... there is a wmb in the unlock path, I suppose on all platforms,
and iirc, ppc & ppc64 implementation of config space accesses do a full
sync. On x86, they are IO ports, thus I would expect them to be fully
sychronous, but I can't guarantee that semantic is respected accross all
architectures.
prev parent reply other threads:[~2005-12-17 6:00 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <200512161959.jBGJxh05007356@hera.kernel.org>
2005-12-16 23:58 ` Benjamin Herrenschmidt
2005-12-17 3:24 ` Alan Stern
2005-12-17 5:55 ` Benjamin Herrenschmidt [this message]
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