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Subject: RE: Problems with EDAC coexisting with BIOS
From: Alan Cox <alan@lxorguk.ukuu.org.uk>
To: "Ong, Soo Keong" <soo.keong.ong@intel.com>
Cc: "Gross, Mark" <mark.gross@intel.com>,
       bluesmoke-devel@lists.sourceforge.net,
       LKML <linux-kernel@vger.kernel.org>,
       "Carbonari, Steven" <steven.carbonari@intel.com>,
       "Wang, Zhenyu Z" <zhenyu.z.wang@intel.com>
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Date: Mon, 24 Apr 2006 15:13:46 +0100
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On Llu, 2006-04-24 at 21:59 +0800, Ong, Soo Keong wrote:
> Alan,
> 
> Have you understood how the errors are connected to the interrupts
> (either SMI, NMI, SCI)?

I believe so

> When does EDAC read the error status? Periodical or upon interrpt by
> errors?

Periodically currently. The sf development tree has some code for
handling the NMI case but this isn't actually useful because an NMI can
occur half way through a PCI config transaction.

Alan