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charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjI5MDA5MSBTYWx0ZWRfXxV1GeMbx1rDK nnnTN6WMPwX084UmCGNBrnFHij4FmgCg9utDrbg8ECo9w4FVfElYOvae2kOV8lpVhG9kZ73pfx+ QsRbrkOod0RE3U/pUrBUw7NTU2AaUWDO4N8CeTbzNa8uJiwN+KsyuwrGvrAf7nb0sRKaC0FuEb4 jDGMCnXNHOySLMRhwuRNh5suNsB7AsX8GfY9sccZjrcXGyhG50sOtxOTs2EYoQM3SRVU/T7xiuQ C0Mfyg8d3f5SM55hYH3AEbM0ddk0czHsckf1F9HmlMxxbM1ly0g96KMb/C0+0KRxKliLJBRPgmo 1AgkhmxBf673/3tOJAjz5jgwvEiWIyDGB0ry2qUj2Hk2GXn1itnVBlX77LwXDDkyQZWlFqsK5GE p2SI2uKkZTJW+xdd3IOwLj4CLx0M3fAZ+IrMz5zRALqf3M/E7Vn/obdh4Sjo0z+qBP800eML5w1 G96/ficKks1IlpLc9uQ== X-Proofpoint-GUID: JJ5aTp2lhzkdC49lteiIvo5PlNJJhbNI X-Proofpoint-ORIG-GUID: JJ5aTp2lhzkdC49lteiIvo5PlNJJhbNI X-Proofpoint-Spam-Info: AW1haW4tMjYwNjI5MDA5MSBTYWx0ZWRfX05R+7Aep4Kxp 89x7xLXF9+puHUjsKqIWliprnbVjeZhzQPnXVImVIxezKqTGBd5JmAAJ1UQbcibpXUYWRpE08zg 6fH/XDryIsxYshtz13QyuPKsCSQwEnQ= X-Authority-Analysis: v=2.4 cv=OcWoyBTY c=1 sm=1 tr=0 ts=6a4252ce cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=DhQjvcdHTzzIjdopfFIA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-29_03,2026-06-26_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 adultscore=0 spamscore=0 clxscore=1015 phishscore=0 bulkscore=0 suspectscore=0 impostorscore=0 malwarescore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2606290091 On 29-06-2026 03:21 pm, Konrad Dybcio wrote: > On 6/29/26 8:43 AM, Imran Shaik wrote: >> >> >> On 25-06-2026 02:14 pm, Konrad Dybcio wrote: >>> On 6/4/26 7:26 AM, Imran Shaik wrote: >>>> Add support for Display clock controller and GPU clock controller nodes >>>> on Qualcomm Shikra SoCs. >>>> >>>> Signed-off-by: Imran Shaik >>>> --- > > [...] > >>>> +                      "gcc_disp_gpll0_clk_src", >>>> +                      "gcc_disp_gpll0_div_clk_src", >>>> +                      "dsi0_phy_pll_out_byteclk", >>>> +                      "dsi0_phy_pll_out_dsiclk", >>>> +                      "dsi1_phy_pll_out_byteclk", >>>> +                      "dsi1_phy_pll_out_dsiclk", >>>> +                      "sleep_clk"; >>>> +            #clock-cells = <1>; >>>> +            #reset-cells = <1>; >>>> +            #power-domain-cells = <1>; >>> >>> DISP_CC also needs to source power from somewhere! >>> >> >> The Shikra bindings aligns with the existing Agatti bindings, as it is a re-use. And the Shikra/Agatti DISPCC is on CX rail, and it will be always ON when APPS is active. > > Yes, it will be on, but currently the genpd performance state requests > (i.e. RPMH states) go to /dev/null because DISP_CC is an orphan > Sure, will check and add the power-domains support as well in the bindings and update the DT accordingly for Shikra and Agatti both. Thanks, Imran