From: Alan Cox <alan@lxorguk.ukuu.org.uk>
To: Alan Stern <stern@rowland.harvard.edu>
Cc: Kernel development list <linux-kernel@vger.kernel.org>
Subject: Re: Flushing writes to PCI devices
Date: Wed, 20 Sep 2006 23:39:16 +0100 [thread overview]
Message-ID: <1158791956.11109.40.camel@localhost.localdomain> (raw)
In-Reply-To: <Pine.LNX.4.44L0.0609201423480.7265-100000@iolanthe.rowland.org>
Ar Mer, 2006-09-20 am 14:28 -0400, ysgrifennodd Alan Stern:
> I've heard that to insure proper synchronization it's necessary to flush
> MMIO writes (writel, writew, writeb) to PCI devices by reading from the
> same area. Is this equally true for I/O-space writes (inl, inw, inb)?
writel/writew/writeb may be posted and delayed until a read from that
device. The outb/outw/outl operations are not posted but are
synchronous.
There may be posting in action both ways (your read may force not only
the write to complete but pending writes the other end). That usually
doesn't matter but very occasionally requires care.
> What about configuration space writes (pci_write_config_dword etc.)?
Usually this is entirely synchronous to PCI bus activity and main
memory. Occasionally chipsets get it slightly wrong
next prev parent reply other threads:[~2006-09-20 22:15 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <fa.gbsNbubc34pqWPOxWCntrwUyt68@ifi.uio.no>
2006-09-20 18:28 ` Alan Stern
2006-09-20 19:10 ` linux-os (Dick Johnson)
[not found] ` <fa.V4O8HKrhUddxYm5+ixVbyZzPybE@ifi.uio.no>
2006-09-20 19:41 ` Bill Waddington
2006-09-20 20:17 ` linux-os (Dick Johnson)
2006-09-21 18:14 ` Bryan O'Sullivan
2006-09-21 18:45 ` Alan Cox
2006-09-21 20:56 ` Roland Dreier
2006-09-21 21:04 ` Bryan O'Sullivan
2006-09-20 22:39 ` Alan Cox [this message]
2006-09-20 23:22 ` Robert Hancock
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